LOGIC PARTITIONING IN VLSI CHIPS TO IMPROVE FAILURE ANALYSIS.

A method is described to speed up the failure analysis of chip defects on very large-scale integrated (VLSI) chips by partitioning the logic. The time required to analyze defects on VLSI chips due to the increasing number of devices on a chip can be a problem. One of the physical design concepts that is being employed to make this complexity more manageable is called a macro design concept. Logic is broken up into partitions, such as an ALU, ROS, or an incrementer. As these macros become larger, the ability to quickly find a defect decreases. In the new technique, all logic macro outputs that would not normally go to a latch when connected to another logic macro are forced to go to a latch.