ChipPRISM: clock routing and timing analysis for high-performance CMOS VLSI chips

This paper describes a new layout system for high-performance CMOS VLSI chips used in supercomputers, focusing on skew-less clock tree generation and accurate timing analysis. In ChipPRISM, a chip is divided into several blocks by floorplanning. Each block is laid out based on standard cells. A clock tree is generated based on a modified H-tree structure which is suitable for asymmetric clock-pin arrangements. This H-tree is routed with an even balance to minimize skew, even when it extends over several blocks in a chip. Timing analysis performs basic delay calculations and path delay calculations to calculate all paths exhaustively and quickly. High-accuracy timing analysis is accomplished by considering the input waveform slope at each gate. ChipPRISM has been used to lay out the chips of the VPP300-series office supercomputers, which are made using 0.35-micron CMOS technology. The new layout system also improves the accuracy of clock cycle prediction.