MATCHING-BASED METHODS FOR HIGH-PERFORMANCE CLOCK ROUTING

Minimizing clock skew is important in the design of high performance VLSI systems. We present a general clock routing scheme that achieves very small clock skews while still using a reasonable amount of wirelength. Our routing solution is based on the construction of a binary tree using geometric matching. For cell-based designs, the total wirelength of our clock routing tree is on average within a constant factor of the wirelength in an optimal Steiner tree, and in the worst case is bounded by O(square-root l1l2 . square-root n) for n terminals arbitrarily distributed in the l1 x l2 grid. The bottom-up construction readily extends to general cell layouts, where it also achieves essentially zero clock skew within reasonably bounded total wirelength. We have tested our algorithms on numerous random examples and also on layouts of industrial benchmark circuits. The results are promising: our clock routing yields near-zero average clock skew while using total wirelength competitive with previously known methods.