A Clock Methodology for High-Performance Microprocessors

This paper discusses an effective clock methodology for the design of high-performance microprocessors. Key attributes include the clustering and balancing of clock loads, multiple clock domains, a balanced clock router with variable width wires to minimize skew, hierarchical clock wiring, automated verification, an interface to the Cadence Design Framework II™ environment, and a complete network model of the clock distribution, including loads. This clock methodology enabled creation of the entire clock network, including verification, in less than three days with approximately 180 ps of skew.