共 50 条
- [41] Designing multiple scan chains for systems-on-chip ATS 2003: 12TH ASIAN TEST SYMPOSIUM, PROCEEDINGS, 2003, : 424 - 427
- [42] Using a single input to support multiple scan chains 1998 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN: DIGEST OF TECHNICAL PAPERS, 1998, : 74 - 78
- [43] Configuring multiple boundary scan chains for interconnect testing ICEMI'2003: PROCEEDINGS OF THE SIXTH INTERNATIONAL CONFERENCE ON ELECTRONIC MEASUREMENT & INSTRUMENTS, VOLS 1-3, 2003, : 961 - 965
- [45] Multiple scan chain design technique for power reduction during test application in BIST 18TH IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS, 2003, : 191 - 198
- [46] Logic BIST with scan chain segmentation INTERNATIONAL TEST CONFERENCE 2004, PROCEEDINGS, 2004, : 57 - 66
- [47] Application of deterministic logic BIST on industrial circuits JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2001, 17 (3-4): : 351 - 362
- [48] Efficient pattern mapping for deterministic logic BIST INTERNATIONAL TEST CONFERENCE 2004, PROCEEDINGS, 2004, : 48 - 56
- [49] Deterministic logic BIST for transition fault testing IET COMPUTERS AND DIGITAL TECHNIQUES, 2007, 1 (03): : 180 - 186
- [50] Application of Deterministic Logic BIST on Industrial Circuits Journal of Electronic Testing, 2001, 17 : 351 - 362