Application of deterministic logic BIST on industrial circuits

被引：9
|
作者：
Kiefer, G
Vranken, H
Marinissen, EJ
Wunderlich, HJ
机构：
[1] Univ Stuttgart, Comp Architecture Lab, D-70565 Stuttgart, Germany
[2] Philips Res Labs, IC Design Digital Design & Test, NL-5656 AA Eindhoven, Netherlands
来源：
JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS | 2001年 / 17卷 / 3-4期
关键词：
logic BIST; industrial applications; scan-based BIST;
D O I：
10.1023/A:1012283800306
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
We present the application of a deterministic logic BIST scheme based on bit-flipping on state-of-the-art industrial circuits. Experimental results show that complete fault coverage can be achieved for industrial circuits up to 100 K gates with 10,000 test patterns, at a total area cost for BIST hardware of typically 5-15%. It is demonstrated that a trade-off is possible between test quality, test time, and silicon area. In contrast to BIST schemes based on test point insertion no modifications of the circuit under test are required, complete fault efficiency is guaranteed, and the impact on the design process is minimized.
引用
收藏
页码：351 / 362
页数：12
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