Efficient compression and application of deterministic patterns in a logic BIST architecture

We present a novel method to efficiently generate, compress and apply test patterns in a logic BIST architecture. Patterns are generated by a modified automatic test pattern generator (ATPG) and are encoded as linear feedback shift register (LFSR) initial values (seeds); one or more patterns can be encoded into a single LFSR seed. During test application, seeds are loaded into the LFSR with no cycle overhead. The method presented achieves reductions of at least 100x in test data and I Ox in tester cycles compared to deterministic ATPG while. maintaining complete fault coverage, as confirmed by experimental results on industrial designs.