Survey on built-in self-test and built-in self-repair of embedded memories

Built-in self-test (BIST) is considered as an efficient approach for embedded memories testing. This paper gives a survey on the up-to-date development of research in this field. It begins with an overview of conventional fault models for memories so far. The inductive fault analysis approach and some new fault models such as read disturb fault and incorrect read fault are discussed. The typical BIST schemes for embedded memories are analyzed. The feasibility of adding built-in redundancy analysis, built-in self-diagnosis and built-in self-repair into BIST circuits is analyzed.