Device simulation with quasi three-dimensional temperature analysis for short-channel poly-Si thin-film transistor

被引：0

作者：

Shimatani, Tamio ^{[1
]}

Matsumoto, Takuji ^{[1
]}

Hashimoto, Takeshi ^{[1
]}

Kato, Noriji ^{[1
]}

Yamada, So ^{[1
]}

Koyanagi, Mitsumasa ^{[1
]}

机构：

[1] Hiroshima Univ, Higashi-Hiroshima, Japan

来源：

Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers | 1994年 / 33卷 / 1 B期

关键词：

Grain boundaries - Semiconducting silicon - Substrates - Thermal conductivity of solids - Thermal effects - Thermoanalysis - Thin film devices - Three dimensional - Transistors;

D O I：

暂无

中图分类号：

学科分类号：

摘要：

A new poly-Si thin-film transistor (TFT) device simulator for quasi three-dimensional temperature analysis has been developed. In this simulator, the influences of the grain boundaries are incorporated into the mobility model when the basic semiconductor equations are solved. Furthermore, we have taken into account the self-heating effect owing to a small thermal conductivity of the insulating substrate using quasi three-dimensional temperature analysis. We could accurately analyze the temperature rise effect and the avalanche short-channel effect in the short-channel poly-Si TFT.

引用

页码：619 / 622

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