共 50 条
- [31] CMOS design of a four-quadrant multiplier based on a novel squarer circuit [J]. Analog Integrated Circuits and Signal Processing, 2014, 80 : 473 - 481
- [34] A low-voltage, low-power, high-linearity CMOS four-quadrant analog multiplier [J]. 2007 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN, VOLS 1-3, 2007, : 751 - +
- [37] A 1.2-V CMOS four-quadrant analog multiplier [J]. 1999 SOUTHWEST SYMPOSIUM ON MIXED-SIGNAL DESIGN, SSMSD 99, 1999, : 1 - 4
- [38] A New CMOS Four-quadrant Analog Multiplier with Differential Output [J]. 2015 INTERNATIONAL CONFERENCE ON SYNTHESIS, MODELING, ANALYSIS AND SIMULATION METHODS AND APPLICATIONS TO CIRCUIT DESIGN (SMACD), 2015,
- [39] FOUR-QUADRANT CMOS ANALOG MULTIPLIER BASED ON NEW CURRENT SQUARER CIRCUIT WITH HIGH-SPEED [J]. EUROCON 2009: INTERNATIONAL IEEE CONFERENCE DEVOTED TO THE 150 ANNIVERSARY OF ALEXANDER S. POPOV, VOLS 1- 4, PROCEEDINGS, 2009, : 282 - 286
- [40] Low-voltage CMOS four-quadrant analogue multiplier for RF applications [J]. ELECTRONICS LETTERS, 1998, 34 (24) : 2285 - 2286