VERIFICATION AND OPTIMIZATION FOR LSI & PCB LAYOUT.

被引：0
|
作者：
Brady, H.Nelson
Smith II, Robert J.
机构：
来源：
Proceedings - Design Automation Conference | 1981年
关键词：
PRINTED CIRCUITS - Computer Aided Design;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
Layout optimization involves interconnection wiring modifications, which improve aesthetic appearance, fabrication characteristics, routability, and reliability of routed boards/chips. Requirements and capabilities of a general purpose layout optimizer are presented, then organization and processing flow of the progam are outlined. The functional decomposition and modular structure of this system are presented. Results achieved by using the verifier/optimizer on large printed circuit boards and gate arrays are given.
引用
收藏
页码：365 / 371
相关论文
共 50 条
  • [41] LSI LAYOUT BY AN ADVANCED FIXED PATTERN APPROACH
    KUBO, M
    KOZAWA, T
    FUJITA, M
    NAGATA, M
    ELECTRICAL ENGINEERING IN JAPAN, 1971, 91 (04) : 1 - &
  • [42] A resizing algorithm for LSI layout with diagonal edges
    Nagao, A
    Kambe, T
    ELECTRONICS AND COMMUNICATIONS IN JAPAN PART III-FUNDAMENTAL ELECTRONIC SCIENCE, 2001, 84 (05): : 62 - 74
  • [43] A novel tool for optimization and verification of layout and human logistics in digital factories
    Mardberg, Peter
    Fredby, Jessica
    Engstrom, Klas
    Li, Yi
    Bohlin, Robert
    Berglund, Jonatan
    Carlson, Johan S.
    Vallhagen, Johan
    51ST CIRP CONFERENCE ON MANUFACTURING SYSTEMS, 2018, 72 : 545 - 550
  • [44] A resizing algorithm for LSI layout with diagonal edges
    Sharp Corporation, Tenri 632, Japan
    Electronics and Communications in Japan, Part III: Fundamental Electronic Science (English translation of Denshi Tsushin Gakkai Ronbunshi), 2001, 84 (05): : 62 - 74
  • [45] LAYOUT - PARTITIONING METHOD FOR MSI AND LSI.
    Brinkmann, K.D.
    Mlynski, D.A.
    Proceedings - IEEE International Symposium on Circuits and Systems, 1977, : 160 - 163
  • [46] AUTOMATIC LAYOUT SYSTEM FOR MASTERSLICE LSI - MARC
    UEDA, K
    SUGIYAMA, Y
    WADA, K
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1978, 13 (05) : 716 - 721
  • [47] STATE-OF-THE-ART: YOU VS COMPUTER-AIDED PIPING LAYOUT.
    O'Keefe, William
    Reason, John
    1984, (128)
  • [48] HIERARCHICAL LAYOUT VERIFICATION
    WAGNER, TJ
    IEEE DESIGN & TEST OF COMPUTERS, 1985, 2 (01): : 31 - 37
  • [49] Layout designs for robotic PCB assembly
    Wang, Collin
    Integrated Manufacturing Systems, 1996, 7 (04): : 39 - 52
  • [50] PCB LAYOUT DESIGN ON WINDOWS NT
    QUANTRELL, D
    ELECTRONIC ENGINEERING, 1994, 66 (813): : S11 - S11
12345