VERIFICATION AND OPTIMIZATION FOR LSI & PCB LAYOUT.

被引：0
|
作者：
Brady, H.Nelson
Smith II, Robert J.
机构：
来源：
Proceedings - Design Automation Conference | 1981年
关键词：
PRINTED CIRCUITS - Computer Aided Design;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
Layout optimization involves interconnection wiring modifications, which improve aesthetic appearance, fabrication characteristics, routability, and reliability of routed boards/chips. Requirements and capabilities of a general purpose layout optimizer are presented, then organization and processing flow of the progam are outlined. The functional decomposition and modular structure of this system are presented. Results achieved by using the verifier/optimizer on large printed circuit boards and gate arrays are given.
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页码：365 / 371
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