MEMORY COMPATIBLE LOGIC SCHEME FOR JOSEPHSON TUNNELING MEMORIES.

被引：0
|
作者：
Herrell, D.J.
Landman, B.S.
Zappe, H.H.
机构：
来源：
| 1607年 / 18期
关键词：
Compendex;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
DATA STORAGE, CRYOELECTRIC
引用
收藏
相关论文
共 50 条
  • [21] SUBNANOSECOND JOSEPHSON TUNNELING MEMORY CELL WITH NONDESTRUCTIVE READOUT
    ZAPPE, HH
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1975, SC10 (01) : 12 - 19
  • [22] Popular Music Memories. Places and Practices of Popular Music Heritage, Memory and Cultural Identity
    Wasserbauer, Marion
    VOLKSKUNDE, 2015, 116 (02): : 248 - 250
  • [23] Japan's Contested Memories. The 'Memory Rifts' in Historical Consciousness of World War II
    Ben-Ari, Eyal
    SOCIAL SCIENCE JAPAN JOURNAL, 2008, 11 (01) : 143 - 146
  • [24] Logic Compatible High-Performance Ferroelectric Transistor Memory
    Dutta, Sourav
    Ye, Huacheng
    Khandker, Akif A.
    Kirtania, Sharadindu Gopal
    Khanna, Abhishek
    Ni, Kai
    Datta, Suman
    IEEE ELECTRON DEVICE LETTERS, 2022, 43 (03) : 382 - 385
  • [25] Logic Synthesis for In-Memory Computing using Resistive Memories
    Shirinzadeh, Saeideh
    Drechsler, Rolf
    2018 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI), 2018, : 375 - 380
  • [26] Protected 0-π states in SIsFS junctions for Josephson memory and logic
    Bakurskiy, S. V.
    Klenov, N. V.
    Soloviev, I. I.
    Pugach, N. G.
    Kupriyanov, M. Yu.
    Golubov, A. A.
    APPLIED PHYSICS LETTERS, 2018, 113 (08)
  • [27] NONVOLATILE, NDRO, ARRAY LOGIC MEMORY CELL IN JOSEPHSON TECHNOLOGY.
    Terlep, K.D.
    IBM Technical Disclosure Bulletin, 1974, 17 (03): : 890 - 891
  • [28] Custom Memory Design for Logic-in-Memory: Drawbacks and Improvements over Conventional Memories
    Ottati, Fabrizio
    Turvani, Giovanna
    Masera, Guido
    Vacca, Marco
    ELECTRONICS, 2021, 10 (18)
  • [29] Logic-in-memory application of CMOS compatible silicon nitride memristor
    Kim, Dahye
    Kim, Sunghun
    Kim, Sungjun
    CHAOS SOLITONS & FRACTALS, 2021, 153
  • [30] An Asynchronous Updating Scheme for a Cellular Logic Memory Array
    Isokawa, Teijiro
    Ishibashi, Shoji
    Minemoto, Toshifumi
    Matsui, Nobuyuki
    Peper, Ferdinand
    2016 FOURTH INTERNATIONAL SYMPOSIUM ON COMPUTING AND NETWORKING (CANDAR), 2016, : 254 - 257
12345