Performance analysis of a new CMOS output buffer

被引：0
|
作者：
机构：
[1] Mahendranath, B.
[2] Srinivasulu, Avireni
来源：
| 1600年 / IEEE Computer Society卷
关键词：
Switching;
D O I：
10.1109/ICCPCT.2013.6529041
中图分类号：
TN3 [半导体技术]; TN4 [微电子学、集成电路（IC）];
学科分类号：
0805 ; 080501 ; 080502 ; 080903 ; 1401 ;
摘要：
A new CMOS output buffer with low switching noise and load adaptability is presented in this paper. The proposed circuit consists of two stages; first stage is set to reduce switching noise, static power dissipation and also output ringing. The second stage involves enough speed and full dynamic range. The performance of the proposed circuit is examined using Cadence and the model parameters of a 180 nm CMOS process. The simulation results have confirmed that the proposed output buffer can reduce propagation delay compared with the previous designs. The topology reports low sensitivities and has features suitable for VLSI implementation. © 2013 IEEE.
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