Study on leakage power estimation and reduction methodology of CMOS circuit

被引：0
|
作者：
Chen, Zhi-Qiang [1 ]
Wu, Xiao-Bo [1 ]
Yan, Xiao-Lang [1 ]
机构：
[1] Institute of VLSI Design, Zhejiang University, Hangzhou 310027, China
来源：
Zhejiang Daxue Xuebao (Gongxue Ban)/Journal of Zhejiang University (Engineering Science) | 2006年 / 40卷 / 05期
关键词：
D O I：
10.1111/j.1525-1438.2006.00385.x
中图分类号：
学科分类号：
摘要：
引用
收藏
页码：772 / 776
相关论文
共 50 条
  • [41] Leakage Power Reduction for Domino Circuits in 45nm CMOS Technologies
    Pandey, A. K.
    Kaur, S.
    Mishra, R. A.
    Nagaria, R. K.
    2012 2ND INTERNATIONAL CONFERENCE ON POWER, CONTROL AND EMBEDDED SYSTEMS (ICPCES 2012), 2012,
  • [42] Body-Bootstrapped-Buffer Circuit for CMOS Static Power Reduction
    Loy, Liang-Yu
    Zhang, Weijia
    Kong, Zhi-Hui
    Goh, Wang-Ling
    Yeo, Kiat-Seng
    2008 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS 2008), VOLS 1-4, 2008, : 842 - 845
  • [43] Estimation of short-circuit power dissipation for static CMOS gates
    Hirata, A
    Onodera, H
    Tamaru, K
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 1996, E79A (03) : 304 - 311
  • [44] Leakage Power Estimation of Adiabatic Circuits Using SPICE in Nanometer CMOS Processes
    Wu, Yang Bo
    Hu, Jian Ping
    Li, Hong
    PROGRESS IN MEASUREMENT AND TESTING, PTS 1 AND 2, 2010, 108-111 : 625 - 630
  • [45] Leakage Power Reduction in CMOS Logic Circuits Using Stack ONOFIC Technique
    Kumar, Chanchal
    Mishra, Avinash Sharan
    Sharma, Vijay Kumar
    PROCEEDINGS OF THE 2018 SECOND INTERNATIONAL CONFERENCE ON INTELLIGENT COMPUTING AND CONTROL SYSTEMS (ICICCS), 2018, : 1363 - 1368
  • [46] SHORT-CIRCUIT POWER DISSIPATION ESTIMATION FOR CMOS LOGIC GATES
    VEMURU, SR
    SCHEINBERG, N
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-FUNDAMENTAL THEORY AND APPLICATIONS, 1994, 41 (11): : 762 - 765
  • [47] Process variation-aware estimation of static leakage power in nano CMOS
    Harish, B. P.
    Bhat, Navakanta
    Patil, Mahesh B.
    SISPAD 2007: SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES 2007, 2007, : 393 - +
  • [48] Power Dissipation Analysis of Adiabatic Circuits and Active Leakage Power Estimation in Nanometer CMOS Processes
    Zhang, Weiqiang
    Su, Li
    Ye, Lifang
    Hu, Jianping
    NANOTECHNOLOGY AND COMPUTER ENGINEERING, 2010, 121-122 : 97 - 102
  • [49] Enhanced Reduction of Ground Bounce Noise in Low Leakage CMOS Multiplier with Combinational MTCMOS Circuit
    Verma, Bipin Kumar
    Singh, Sham Babu
    Akashe, Sham
    2013 IEEE INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING, COMPUTING AND CONTROL (ISPCC), 2013,
  • [50] Power estimation and reduction of CMOS circuits considering gate delay
    Ueda, H
    Kinoshita, K
    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 1999, E82D (01) : 301 - 308
12345