Direct tunneling gate current of MOSFET and its impact on CMOS logic circuit

被引：0
|
作者：
机构：
[1] [1,Tang, Dongfeng
[2] Zhang, Ping
[3] Long, Zhilin
[4] Hu, Shigang
[5] Wu, Xiaofeng
来源：
Tang, D. (dftang@hnust.edu.cn) | 1600年 / Central South University of Technology卷 / 44期
关键词：
CMOS integrated circuits - Integrated circuit manufacture - Metals - Leakage currents - Metallic compounds - Logic circuits - Oxide semiconductors - SPICE - MOS devices - Dielectric devices - Gates (transistor) - Timing circuits - Computer circuits - Electric breakdown;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
引用
收藏
相关论文
共 50 条
  • [41] Effects of gate-to-body tunneling current on PD/SOI CMOS SRAM
    Joshi, RV
    Chuang, CT
    Fung, SKH
    Assaderaghi, F
    Sherony, M
    Yang, I
    Shahidi, G
    2001 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2001, : 75 - 76
  • [42] Effects of gate-to-body tunneling current on PD/SOI CMOS latches
    Chuang, CT
    Puri, R
    2003 IEEE INTERNATIONAL CONFERENCE ON SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES, 2003, : 291 - 294
  • [43] Cascadable direct current driven skyrmion logic inverter gate
    Cheghabouri, Arash Mousavi
    Katmis, Ferhat
    Onbasli, Mehmet C.
    PHYSICAL REVIEW B, 2022, 105 (05)
  • [44] Theoretical study of the SiO2/Si interface and its effect on energy band profile and MOSFET gate tunneling current
    Zhu Huiwen
    Liu Yongsong
    Mao Lingfeng
    Shen Jingqin
    Zhu Zhiyan
    Tang Weihua
    JOURNAL OF SEMICONDUCTORS, 2010, 31 (08)
  • [45] Theoretical study of the SiO2/Si interface and its effect on energy band profile and MOSFET gate tunneling current
    朱晖文
    刘咏松
    毛凌峰
    沈静琴
    朱志艳
    唐为华
    半导体学报, 2010, 31 (08) : 11 - 15
  • [46] High Current Gate Drive Circuit with High Temperature Potential for SiC MOSFET Module
    Qi, Feng
    Xu, Longya
    Zhao, Bo
    Zhou, Zhe
    2015 IEEE ENERGY CONVERSION CONGRESS AND EXPOSITION (ECCE), 2015, : 7031 - 7037
  • [47] Modeling of direct tunneling current in multi-layer gate stacks
    Dunga, MV
    Xi, XM
    He, J
    Polishchuk, I
    Lu, Q
    Chan, MS
    Niknejad, AM
    Hu, CM
    NANOTECH 2003, VOL 2, 2003, : 306 - 309
  • [48] A Novel Noise Margin Model of Surrounding-gate MOSFET Working on Subthreshold CMOS Logic Gates
    Chiang, Te-Kuang
    Chen, Chih Yo
    Gao, Hong-Wun
    Wang, Yeong-Her
    7TH IEEE INTERNATIONAL NANOELECTRONICS CONFERENCE (INEC) 2016, 2016,
  • [49] Analog IC Design in Ultra-Thin Oxide CMOS Technologies With Significant Direct Tunneling-Induced Gate Current
    Bohannon, Eric
    Washburn, Clyde
    Mukund, P. R.
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2011, 58 (04) : 645 - 653
  • [50] Back-gate bias Effect on the MOSFET-C CMOS UTBB Performance by Circuit Simulations
    Martinez, A.
    Alvarado, J.
    Kilchytska, V.
    Alcantara, S.
    Flandre, D.
    2019 JOINT INTERNATIONAL EUROSOI WORKSHOP AND INTERNATIONAL CONFERENCE ON ULTIMATE INTEGRATION ON SILICON (EUROSOI-ULIS), 2019,
12345