Effective instruction fetch control mechanism for SMT processors

被引:0
|
作者
College of Computer Science, Inner Mongolia University, Huhhot 010021, China [1 ]
不详 [2 ]
不详 [3 ]
机构
来源
Jisuanji Xuebao | 2006年 / 4卷 / 535-543期
关键词
22;
D O I
暂无
中图分类号
学科分类号
摘要
引用
收藏
相关论文
共 50 条
  • [31] Effective Instruction Fetch Stage Design for 16-bit Instruction Set Architecture
    Kim, Areum
    Hwang, Seok Joong
    Kim, Seon Wook
    8TH IEEE INTERNATIONAL CONFERENCE ON COMPUTER AND INFORMATION TECHNOLOGY WORKSHOPS: CIT WORKSHOPS 2008, PROCEEDINGS, 2008, : 563 - 568
  • [32] Guaranteeing Instruction Fetch Behavior with a Lookahead Instruction Fetch Engine (LIFE)
    Hines, Stephen
    Peress, Yuval
    Gavin, Peter
    Whalley, David
    Tyson, Gary
    ACM SIGPLAN NOTICES, 2009, 44 (07) : 119 - 128
  • [33] Adaptive instruction dispatching techniques for Simultaneous Multi-Threading (SMT) processors
    Debnath, Monobrata
    Lin, Wei-Ming
    John, Eugene
    COMPUTERS & ELECTRICAL ENGINEERING, 2012, 38 (06) : 1616 - 1626
  • [34] Guaranteeing Instruction Fetch Behavior with a Lookahead Instruction Fetch Engine (LIFE)
    Hines, Stephen
    Peress, Yuval
    Gavin, Peter
    Whalley, David
    Tyson, Gary
    LCTES'09: PROCEEDINGS OF THE 2009 ACM SIGPLAN/SIGBED CONFERENCE ON LANGUAGES, COMPILERS, AND TOOLS FOR EMBEDDED SYSTEMS, 2009, : 119 - 128
  • [35] Proactive Instruction Fetch
    Ferdman, Michael
    Kaynak, Cansu
    Falsafi, Babak
    PROCEEDINGS OF THE 2011 44TH ANNUAL IEEE/ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE (MICRO 44), 2011, : 152 - 162
  • [36] A Defense Mechanism Against Transient Execution Attacks On SMT Processors
    Jin, Xin
    Yu, Ningmei
    IEICE ELECTRONICS EXPRESS, 2021,
  • [37] A controlled fetching technique for effective management of shared resources in SMT processors
    Ramanathan, Madhava Krishnan
    Lin, Wei-Ming
    MICROPROCESSORS AND MICROSYSTEMS, 2018, 57 : 42 - 51
  • [38] Fetch gating control through speculative instruction window weighting
    Vandierendonck, Hans
    Seznec, Andre
    HIGH PERFORMANCE EMBEDDED ARCHITECTURES AND COMPILERS, PROCEEDINGS, 2007, 4367 : 120 - +
  • [39] Branch classification to control instruction fetch in Simultaneous Multithreaded architectures
    Knijenburg, PMW
    Ramirez, A
    Latorre, F
    Larriba, J
    Valero, M
    INTERNATIONAL WORKSHOP ON INNOVATIVE ARCHITECTURE FOR FUTURE GENERATION HIGH-PERFORMANCE PROCESSORS AND SYSTEMS, 2002, : 67 - 76
  • [40] Fetch directed instruction prefetching
    Reinman, G
    Calder, B
    Austin, T
    32ND ANNUAL INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE, (MICRO-32), PROCEEDINGS, 1999, : 16 - 27