Programmable logic design line

The IP block, whose function is captured as a registered-transfer-level (RTL)representation, is originally encrypted by third-party IP vendor. This encrypted block is passed to customer's design team, which combines it with other IP blocks and with its own custom-generated RTL to create a representation of the entire design. The team uses synthesis tools from an EDA vendor to translate this design into a gate-level netlist. Later, they will use the place-and-route tools provided by the FPGA vendor to generate the configuration bit stream that will be used to configure(program) the FPGA. The encrypted IP block may be used by multiple EDA tools-such as synthesis and simulation. In case of synthesis, the IP block is first decrypted and then synthesized, along with any unprotected portions of the design. The ensuing netlist or the portions of the netlist representing the protected IP functions will be re-encrypted before being fed forward to the FPGA vendor's tools.