Several high-speed and low-consumption BiCMOS OC gates and their wired-AND logic systems

To meet the application needs of high-speed and low-energy consumption digital systems, several kinds of BiCMOS open collector (OC) gates were designed by means of modifying inner structure and by using optimal parameters, with which some wired-AND logic systems were connected, and the common upward-resistance RL expressions of these systems were deduced from 2 wired-AND equivalent circuits. The related analysis, simulation and the circuit experiment results have shown that the designed BiCMOS wired-AND logic systems can work properly within 2.6-4.0 V, the average speed is close to that of conventional TTL OC gate, the power consumption is lower than that of the conventional gate by 4.77-5.68 mW, and the delay-consumption product is reduced by an average of 45.5% as compared to the conventional gate at 60 MHz.