Near-threshold adiabatic SRAM based on CPAL circuits with DTCMOS technique

An adiabatic SRAM (Static Random access memory) operating in near-threshold region based on CPAL (Complementary pass-transistor adiabatic logic) circuits with DTCMOS (dual-threshold CMOS) technique is realized for low-energy applications. The SRAM using the CPAL circuits can recover the energy of the read driver, write driver circuit, word-line decoder, and sense amplifier in a fully adiabatic manner. The DTCMOS technique can effectively reduce the leakage energy consumption of the SRAM. In addition, near-threshold tech-nique can not only greatly reduce dynamic energy consumption, but also satisfy the requirement of mid-performance systems. Modelling and sizing of adiabatic storage cells are constructed and analysed. The simulations for the function and energy consumption of the SRAM are carried out with a SMIC 130nm CMOS process. The HSPICE simulation results show that the SRAM has ideal logic function and low energy consumption.