Modeling and optimization of power-gating adiabatic circuits for near-threshold computing

A power-gating scheme and its optimization for near-threshold operating of adiabatic circuits are addressed in this paper. CPAL (Complementary pass-transistor logic) circuits are used as the fourphase power-gating switches to reduce the sleep leakage dissipations of the adiabatic circuits. The power-gated logic blocks are realized with CPAL circuits with the dual threshold CMOS technique to reduce active leakage dissipations of the CPAL circuits. The analytical model for power-gating adiabatic circuits is constructed. Based on proposed model parameters, the energy overhead of the proposed power-gating scheme is analyzed in detail. A near-threshold 8-bit full adder based on the CPAL circuits with NCSU PDK 45nm technology is used to verify the proposed power-gating technique. Both active and sleep leakage dissipations are effectively reduced by using the powergating scheme and dual threshold CMOS technique. The results show that the proposed power-gating technique is suitable for the adiabatic units operating on near-threshold region. © Sila Science.