Sequential logic optimization by sequential redundancy addition and removal improved with retiming

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作者：
San Millán, Enrique [1 ]
Entrena, Luis [1 ]
Mengibar, Luis [1 ]
García, Michael [1 ]
机构：
[1] Electronics Technology Department, University Carlos III of Madrid, Butarque 15, E-28911 Leganés Madrid, Spain
来源：
WSEAS Transactions on Circuits and Systems | 2006年 / 5卷 / 08期
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页码：1159 / 1165
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