Instantaneous IPC based instruction fetch policy for SMT processors

被引:0
|
作者
College of Computer Science, Inner Mongolia University, Huhhot 010021, China [1 ]
不详 [2 ]
机构
来源
关键词
Computer architecture - Multiprocessing programs - Multiprocessing systems;
D O I
暂无
中图分类号
学科分类号
摘要
Simultaneous Multithreaded Processors improve the instruction throughput by allowing fetching and executing instructions from several running threads simultaneously in each clock cycle. In this paper, first, the authors introduce simply several instruction fetch policies of SMT processors, and compare their performance on improving IPC of single running workload. Next, an ideal fetch model of instruction fetch policy is given, and a realistic policy named IPCBFP, based on the ideal model, is proposed and analyzed. This policy fetches instructions for a thread according to its instantaneous IPC value and its current instruction number in the instruction queue. Simulation results show that IPCBFP policy can improve the performances of the workloads dramatically. In two-thread and four-thread mix workload experiments, the speedups are 17% and 8% on average respectively. In addition, the sizes and the conflict rates of IQ on average in the experiments with the policy are small than that with ICOUNT. 2.8 policy, which is the best fetch policy up to date to our knowledge. And the authors' policy also has some advantages on the degradation of cache miss rates and TLB miss rates.
引用
收藏
页码:629 / 637
相关论文
共 50 条
  • [1] A resource utilization based instruction fetch policy for SMT processors
    Weng, Lichen
    Liu, Chen
    MICROPROCESSORS AND MICROSYSTEMS, 2015, 39 (01) : 1 - 10
  • [2] Achieving Predictable Performance in SMT Processors by Instruction Fetch Policy
    Sun, Caixia
    Wang, Yongwen
    Xu, Jinbo
    COMPUTER ENGINEERING AND TECHNOLOGY, NCCET 2013, 2013, 396 : 186 - 197
  • [3] Using instruction fetch policy to control performance of a thread in SMT processors
    School of Computer Science, National University of Defense Technology, Changsha 410073, China
    Jisuanji Xuebao, 2008, 2 (309-317):
  • [4] Effective instruction fetch control mechanism for SMT processors
    College of Computer Science, Inner Mongolia University, Huhhot 010021, China
    不详
    不详
    Jisuanji Xuebao, 2006, 4 (535-543):
  • [5] An instruction fetch policy handling L2 cache misses in SMT processors
    Sun, Caixia
    Tang, Hongwei
    Zhang, Minxuan
    EIGHTH INTERNATIONAL CONFERENCE ON HIGH-PERFORMANCE COMPUTING IN ASIA-PACIFIC REGION, PROCEEDINGS, 2005, : 519 - 525
  • [6] Controlling performance of a time-critical thread in SMT processors by instruction fetch policy
    Sun, Caixia
    Tang, Hongwei
    Zhang, Minxuan
    SEVENTH INTERNATIONAL CONFERENCE ON PARALLEL AND DISTRIBUTED COMPUTING, APPLICATIONS AND TECHNOLOGIES, PROCEEDINGS, 2006, : 217 - +
  • [7] DLL-conscious instruction fetch optimization for SMT processors
    Mohamood, Fayez
    Ghosh, Mrinmoy
    Lee, Hsien-Hsin S.
    JOURNAL OF SYSTEMS ARCHITECTURE, 2008, 54 (12) : 1089 - 1100
  • [8] Enhancing DCache warn fetch policy for SMT processors
    Zhang, MX
    Sun, CX
    PARALLEL AND DISTRIBUTED PROCESSING AND APPLICATIONS, 2005, 3758 : 216 - 223
  • [9] An effective instruction fetch policy for simultaneous multithreaded processors
    He, LQ
    Liu, ZY
    SEVENTH INTERNATIONAL CONFERENCE ON HIGH PERFORMANCE COMPUTING AND GRID IN ASIA PACIFIC REGION, PROCEEDINGS, 2004, : 162 - 168
  • [10] A memory-level parallelism aware fetch policy for SMT processors
    Eyerman, Stijn
    Eeckhout, Lieven
    THIRTEENTH INTERNATIONAL SYMPOSIUM ON HIGH-PERFORMANCE COMPUTER ARCHITECTURE, PROCEEDINGS, 2007, : 240 - +