Bit plane-parallel coder for EBCOT and its VLSI architecture

被引：0
|
作者：
Liu, Kai [1 ,2 ]
Wu, Cheng-Ke [1 ]
Li, Yun-Song [1 ]
Zhuang, Huai-Yu [1 ]
机构：
[1] Lab. of Integrated Service Networks, Xidian Univ., Xi'an 710071, China
[2] Sch. of Comp., Xidian Univ., Xi'an 710071, China
来源：
Jisuanji Xuebao/Chinese Journal of Computers | 2004年 / 27卷 / 07期
关键词：
D O I：
暂无
中图分类号：
学科分类号：
摘要：
11
引用
收藏
页码：928 / 935
相关论文
共 50 条
  • [11] A VLSI architecture of EBCOT encoder for JPEG2000
    Liu, LB
    Li, DJ
    Zhang, L
    Wang, ZH
    Chen, HY
    2003 5TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS, 2003, : 882 - 885
  • [12] A parallel skeletonization algorithm and its VLSI architecture
    Sudha, N
    Nandi, S
    FIFTH INTERNATIONAL CONFERENCE ON HIGH PERFORMANCE COMPUTING, PROCEEDINGS, 1998, : 65 - 72
  • [13] VLSI Architecture of Arithmetic Coder Used in SPIHT
    Liu, Kai
    Belyaev, Evgeniy
    Guo, Jie
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2012, 20 (04) : 697 - 710
  • [14] PLANE-PARALLEL FABRICS OF HYPERSURFACE
    BARTOSHEVICH, MA
    DOKLADY AKADEMII NAUK SSSR, 1959, 124 (05): : 970 - 972
  • [15] A plane-parallel plate refractometer
    Pfund, AH
    JOURNAL OF THE OPTICAL SOCIETY OF AMERICA, 1931, 21 (03) : 182 - 186
  • [16] Pass-Parallel VLSI Architecture of BPC for Embedded Block Coder in JPEG2000
    Gavvala, Ramulu
    Chandra, S. Sharath
    Gopal, M. Madana
    Rao, S. Srinivasa
    2012 ASIA PACIFIC CONFERENCE ON POSTGRADUATE RESEARCH IN MICROELECTRONICS & ELECTRONICS (PRIMEASIA), 2012, : 111 - 117
  • [17] DEVICE FOR MAKING PLANE AND PLANE-PARALLEL SPECIMENS
    BALDIN, AV
    MATVIENKO, AF
    RIZNYACHOK, SA
    INDUSTRIAL LABORATORY, 1979, 45 (06): : 690 - 691
  • [18] High speed VLSI architecture for bit plane encoder of JPEG2000
    Gupta, AK
    Taubman, D
    Nooshabadi, S
    2004 47TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II, CONFERENCE PROCEEDINGS, 2004, : 233 - 236
  • [19] VLSI architecture for fast motion estimation based on bit-plane matching
    Ko, YK
    Ko, SJ
    Lee, JW
    Kim, HG
    Oh, HC
    JOURNAL OF THE KOREAN PHYSICAL SOCIETY, 2000, 37 (06) : 938 - 944
  • [20] A parallel architecture for arithmetic coding and its VLSI implementation
    Lee, HY
    Lan, LS
    Sheu, MH
    Wu, CH
    PROCEEDINGS OF THE 39TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I-III, 1996, : 1309 - 1312
12345