A 10 Gb/s equalizer in 0.18μm CMOS technology for high-speed SerDes

被引：0
|
作者：
Zhang, Mingke [1 ]
Hu, Qingsheng [1 ]
机构：
[1] Institute of RF- and OE-ICs, Southeast University, Nanjing, China
来源：
International Journal of Control and Automation | 2014年 / 7卷 / 11期
关键词：
CMOS integrated circuits - Feedback;
D O I：
10.14257/ijca.2014.7.11.28
中图分类号：
学科分类号：
摘要：
A 10 Gb/s equalizer consisting of analog equalizer and two-tap half-rate decision feedback equalizer (DFE) in 0.18μm CMOS has been designer. By employing capacitive degeneration and inductive peaking techniques, the analog equalizer achieves large boosting. The pipelined half-rate architecture is used to improve the transmitted data rate in DFE with a small increase in area. Measurement results show that the distorted signal is well recovered by this equalizer and consumes 27 mW with the supply voltage of 1.8-V. The overall chip area including pads is 0.6×0.7 mm2.
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页码：299 / 302
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