Design of current-mode CMOS pulse-triggered d flip-flops

With the requirements of pulsed-triggered Flip-Flop and the threshold-arithmetic algebraic system, a novel universal structure of current-mode CMOS pulsed-triggered D Flip-Flop is proposed for binary and multi-valued current-mode CMOS pulsed-triggered D Flip-Flops design. Based on the proposed structure, a Binary Current-Mode CMOS pulse-triggered D Flip-Flop (BCMPDFF), a Ternary Current-Mode CMOS Pulse-triggered D Flip-Flop (TCMPDFF) and a Quaternary Current-Mode CMOS Pulse-triggered D Flip-Flop (QCMPDFF) are designed, respectively, and the designed Flip-Flops can be easily incorporated into single and double edge-triggered design. The HSPICE simulation using TSMC 180 nm CMOS technology show that the designed D Flip-Flops based on the proposed universal structure have the correct logic function. The setup time and hold time of the designed Flip-Flops are optimalized, respectively. Comparing to the published current-mode CMOS master-slave D Flip-Flops, the worst minimum D-Q delay of BCMPDFF and QCMPDFF can be reduced by 56.97% and 54.99%, respectively, comparing to the published current-mode CMOS edge-triggered D Flip-Flops, the worst minimum D-Q delay can be reduced by at least 4.26%. The designed Flip-Flops have the advantage of fewer transistors, relatively simpler structure and higher performance.