Design of thermally aware ultra low power clock generator for moderate speed VLSI chip applications

被引:0
|
作者
Walunj R.A. [1 ]
Pable S.D. [1 ]
Kharate G.K. [1 ]
机构
[1] Department of Electronics and Telecommunication, Matoshri College of Engineering and Research Centre, Savitribai Phule Pune University, Nasik
关键词
clock generator; Sub-threshold; thermal stability; Ultra Low Power (ULP); voltage controlled oscillator (VCO);
D O I
10.1080/1448837X.2018.1480305
中图分类号
学科分类号
摘要
Sub-threshold operation of devices provides a promising approach to satisfy the ultra-low power demand of handheld products. However, in this domain, the drive current exponentially depends on temperature which makes the sub-threshold circuits more prone to temperature variations. This paper proposes a scheme to improve the thermal stability of an ultra low power clock generator circuit which is vital for reliable operation of portable synchronous digital VLSI chip applications. In this work, combination of temperature monitoring circuit and control circuit has been incorporated to develop a thermally robust clock generator. A novel control strategy is developed, wherein the control voltage is adaptively altered to combat the exponential change in the clock period with the variation in temperature, without use of any passive components like resistors and capacitors. Simulation results shows that the proposed circuit gives constant clock period against a wide range of temperature variations. The proposed oscillator operates at 0.37V, consumes 1.5µW power and provides a temperature coefficient of 290ppm/°C over a temperature range from 10°C to120°C without any external trimming. ©, © Engineers Australia.
引用
收藏
页码:9 / 20
页数:11
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