Low complex parallel implementation of Turbo decoding

被引：0
|
作者：
Zhang, Z.P. [1 ]
Zhou, L. [1 ]
Jin, F. [1 ]
机构：
[1] Coll. of Commun. and Info. Eng., Univ. of Electron. Sci. and Technol., Chengdu 610054, China
来源：
Tien Tzu Hsueh Pao/Acta Electronica Sinica | 2001年 / 29卷 / 02期
关键词：
Algorithms - Architecture - Computational complexity - Computer simulation - Data flow analysis - Data processing - Data structures - Decoding - Parallel processing systems - Time series analysis - VLSI circuits;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
The Max-LOG-MAP algorithm (MLM) is a simplified version for the decoding of Turbo codes. Architecture of parallel array is suggested based on the MLM algorithm and is easy to implement by VLSI. The data flow directions and the computation procedures of the algorithm structure are obtained, the relations among the nodes and data frames are analyzed and the simple time sequencing of data operations are given. The architecture is justified by computer simulation.
引用
收藏
页码：272 / 274
相关论文
共 50 条
  • [1] A low complex parallel decoding structure for turbo-codes
    Zhang, ZP
    Zhou, L
    2000 INTERNATIONAL CONFERENCE ON COMMUNICATION TECHNOLOGY PROCEEDINGS, VOLS. I & II, 2000, : 312 - 316
  • [2] Low Latency Parallel Turbo Decoding Implementation for Future Terrestrial Broadcasting Systems
    Luo, Hua
    Zhang, Yue
    Li, Wei
    Huang, Li-Ke
    Cosmas, John
    Li, Dayou
    Maple, Carsten
    Zhang, Xun
    IEEE TRANSACTIONS ON BROADCASTING, 2018, 64 (01) : 96 - 104
  • [3] Parallel turbo decoding
    Zhang, Y
    Parhi, KK
    2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 2, PROCEEDINGS, 2004, : 509 - 512
  • [4] BER Guaranteed Optimization and Implementation of Parallel Turbo Decoding on GPU
    Chen, Xiang
    Zhu, Ji
    Wen, Ziyu
    Wang, Yu
    Yang, Huazhong
    2013 8TH INTERNATIONAL ICST CONFERENCE ON COMMUNICATIONS AND NETWORKING IN CHINA (CHINACOM), 2013, : 183 - 188
  • [5] A parallel MAP algorithm for low latency turbo decoding
    Yoon, S
    Bar-Ness, Y
    IEEE COMMUNICATIONS LETTERS, 2002, 6 (07) : 288 - 290
  • [6] FPGA Implementation of Parallel Sorting Mechanism for Turbo Decoding in LTE System
    Sadangi, Sushant
    Priyanka, Priti
    PROCEEDINGS OF THE 2018 SECOND INTERNATIONAL CONFERENCE ON INVENTIVE COMMUNICATION AND COMPUTATIONAL TECHNOLOGIES (ICICCT), 2018, : 359 - 362
  • [7] Parallel decoding of turbo codes
    Chang, Y
    ELECTRONICS LETTERS, 1996, 32 (13) : 1188 - 1189
  • [8] Parallel Decoding of Turbo Codes
    Spasov, Dejan
    ICT INNOVATIONS 2018: ENGINEERING AND LIFE SCIENCES, ICT INNOVATIONS 2018, 2018, 940 : 100 - 106
  • [9] Novel low-delay scheme for parallel Turbo decoding
    Ren, De-Feng
    Ge, Jian-Hua
    Gong, Feng-Kui
    Wang, Yong
    Tongxin Xuebao/Journal on Communications, 2011, 32 (06): : 38 - 44
  • [10] A parallel decoder for low latency decoding of turbo product codes
    Argon, C
    McLaughlin, SW
    IEEE COMMUNICATIONS LETTERS, 2002, 6 (02) : 70 - 72
12345