A novel design of a memristor-based look-up table (LUT) for FPGA

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20153101081328
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(1) Department of Electrical and Electronic Eng., University of Nottingham, Selangor, Malaysia; (2) Department of ECE, Northeastern University, Boston; MA; 02115, United States | 1600年 / IEEE; IEEE Circuits and Systems Society卷 / Institute of Electrical and Electronics Engineers Inc., United States期
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This paper presents a novel scheme for a memristor-based look-up table (LUT); in this scheme the states of the unselected memristors are unaffected by WRITE/READ operations. Therefore; it addresses the prevalent problems associated with nano crossbars; such as the write half-select and sneak path currents. In the proposed scheme the memristors are connected in rows and columns; while the columns are isolated. The new scheme is simulated using LTSPICE IV and extensive results are presented with respect to the WRITE and READ operations. In addition; the performance improvement of the proposed method is compared with previous LUT schemes using memristors as well as SRAM. The results show that proposed scheme is significantly better in terms of delay and Energy Delay Product (EDP) for both the WRITE and READ operations. © 2014 IEEE;
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