A novel design of a memristor-based look-up table (LUT) for FPGA

被引：0
|
作者：
20153101081328
机构：
来源：
(1) Department of Electrical and Electronic Eng., University of Nottingham, Selangor, Malaysia; (2) Department of ECE, Northeastern University, Boston; MA; 02115, United States | 1600年 / IEEE; IEEE Circuits and Systems Society卷 / Institute of Electrical and Electronics Engineers Inc., United States期
关键词：
This paper presents a novel scheme for a memristor-based look-up table (LUT); in this scheme the states of the unselected memristors are unaffected by WRITE/READ operations. Therefore; it addresses the prevalent problems associated with nano crossbars; such as the write half-select and sneak path currents. In the proposed scheme the memristors are connected in rows and columns; while the columns are isolated. The new scheme is simulated using LTSPICE IV and extensive results are presented with respect to the WRITE and READ operations. In addition; the performance improvement of the proposed method is compared with previous LUT schemes using memristors as well as SRAM. The results show that proposed scheme is significantly better in terms of delay and Energy Delay Product (EDP) for both the WRITE and READ operations. © 2014 IEEE;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
112982
引用
收藏
相关论文
共 50 条
  • [31] A test approach for look-up table based FPGAs
    Atoofian, E
    Navabi, Z
    JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY, 2006, 21 (01) : 141 - 146
  • [32] A shifter look-up table technique based on HXDSP
    Ye H.
    Gu N.
    Lin C.
    Zhang X.
    Chen R.
    Beijing Hangkong Hangtian Daxue Xuebao/Journal of Beijing University of Aeronautics and Astronautics, 2019, 45 (10): : 2044 - 2050
  • [33] An optimum ORA BIST for multiple fault FPGA Look-Up Table testing
    Alaghi, Armin
    Yarandi, Mahnaz Sadoughi
    Navabi, Zainalabedin
    PROCEEDINGS OF THE 15TH ASIAN TEST SYMPOSIUM, 2006, : 293 - +
  • [34] A Compact Memristor-CMOS Hybrid Look-Up-Table Design and Potential Application in FPGA
    Guo, Yanwen
    Wang, Xiaoping
    Zeng, Zhigang
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2017, 36 (12) : 2144 - 2148
  • [35] An Energy-Efficient Look-up Table Framework for Super Resolution on FPGA
    Li, Huanan
    Jia, Shicheng
    Guan, Juntao
    Lai, Rui
    Liu, Shubin
    Zhu, Zhangming
    2024 IEEE 6TH INTERNATIONAL CONFERENCE ON AI CIRCUITS AND SYSTEMS, AICAS 2024, 2024, : 527 - 531
  • [36] Analysis of a Novel Non-Volatile Look-Up Table (NV LUT) Controller Design with Resistive Random-Access Memories (RRAM) for Field-Programmable Gate Arrays (FPGA)
    Chee, Hock Leong
    Kumar, T. Nandha
    Almurib, Haider A. F.
    Kang, Desmond Wen Hui
    PROCEEDINGS OF THE 2019 IEEE REGIONAL SYMPOSIUM ON MICRO AND NANOELECTRONICS (RSM), 2019, : 87 - 90
  • [37] Operational Fault Detection and Monitoring of a Memristor-Based LUT
    Kumar, T. Nandha
    Almurib, Haider A. F.
    Lombardi, Fabrizio
    2015 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), 2015, : 429 - 434
  • [38] The 2006 CHF look-up table
    Groeneveld, D. C.
    Shan, J. Q.
    Vasic, A. Z.
    Leung, L. K. H.
    Durmayaz, A.
    Yang, J.
    Cheng, S. C.
    Tanase, A.
    NUCLEAR ENGINEERING AND DESIGN, 2007, 237 (15-17) : 1909 - 1922
  • [39] Look Up Table (LUT) inverse halftoning
    Mese, M
    Vaidyanathan, PP
    ISCAS 2000: IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - PROCEEDINGS, VOL IV: EMERGING TECHNOLOGIES FOR THE 21ST CENTURY, 2000, : 517 - 520
  • [40] Design and demonstration of an optoelectronic look-up table using VCSEL-based logic
    Lurkins, JW
    Irakliotis, LJ
    Stanko, P
    Snyder, RD
    Mitkas, PA
    Wilmsen, CW
    MATERIALS, DEVICES, AND SYSTEMS FOR OPTOELECTRONIC PROCESSING, 1996, 2848 : 167 - 173
12345