A novel design of a memristor-based look-up table (LUT) for FPGA

被引：0
|
作者：
20153101081328
机构：
来源：
(1) Department of Electrical and Electronic Eng., University of Nottingham, Selangor, Malaysia; (2) Department of ECE, Northeastern University, Boston; MA; 02115, United States | 1600年 / IEEE; IEEE Circuits and Systems Society卷 / Institute of Electrical and Electronics Engineers Inc., United States期
关键词：
This paper presents a novel scheme for a memristor-based look-up table (LUT); in this scheme the states of the unselected memristors are unaffected by WRITE/READ operations. Therefore; it addresses the prevalent problems associated with nano crossbars; such as the write half-select and sneak path currents. In the proposed scheme the memristors are connected in rows and columns; while the columns are isolated. The new scheme is simulated using LTSPICE IV and extensive results are presented with respect to the WRITE and READ operations. In addition; the performance improvement of the proposed method is compared with previous LUT schemes using memristors as well as SRAM. The results show that proposed scheme is significantly better in terms of delay and Energy Delay Product (EDP) for both the WRITE and READ operations. © 2014 IEEE;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
112982
引用
收藏
相关论文
共 50 条
  • [21] The circuit designs of an sram based look-up table for high permormane FPGA architecture
    Mal, P
    Cantin, JF
    Beyette, FR
    2002 45TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL III, CONFERENCE PROCEEDINGS, 2002, : 227 - 230
  • [22] A novel table look-up scheme based on GFScom and its application
    Shengli Zhang
    Yongming Li
    Soft Computing, 2017, 21 : 6767 - 6781
  • [23] TABLE LOOK-UP RULE
    HARALICK, RM
    COMMUNICATIONS IN STATISTICS PART A-THEORY AND METHODS, 1976, 5 (12): : 1163 - 1191
  • [24] A novel look-up table design method for data hiding with reduced distortion
    Zhang, Xiao-Ping
    Li, Kan
    Wang, Xiaofeng
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, 2008, 18 (06) : 769 - 776
  • [25] Design of Square Generator with Small Look-up Table
    Tsai, Wei-Chang
    Shieh, Ming-Der
    Lin, Wen-Chin
    Wey, Chin-Long
    2008 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS 2008), VOLS 1-4, 2008, : 172 - +
  • [26] A BIST architecture for FPGA look-up table testing reduces reconfigurations
    Atoofian, E
    Navabi, Z
    ATS 2003: 12TH ASIAN TEST SYMPOSIUM, PROCEEDINGS, 2003, : 84 - 89
  • [27] A Novel Design for a Memristor-Based OR Gate
    Zhang, Yang
    Shen, Yi
    Wang, Xiaoping
    Guo, Yanwen
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2015, 62 (08) : 781 - 785
  • [28] FREAC-LUT: A NEW DYNAMIC LOOK-UP TABLE APPROACH TO SECURE CHAOTIC ENCRYPTION
    Hasimoto-Beltran, Rogelio
    INTERNATIONAL JOURNAL OF BIFURCATION AND CHAOS, 2013, 23 (01):
  • [29] Look-up table-based pulse-shaping filter design
    Kim, MS
    Kim, DI
    Chung, JG
    Lim, MS
    ELECTRONICS LETTERS, 2000, 36 (17) : 1505 - 1506
  • [30] A Test Approach for Look-Up Table Based FPGAs
    Ehsan Atoofian
    Zainalabedin Navabi
    Journal of Computer Science and Technology, 2006, 21 : 141 - 146
12345