A novel mesh-based hierarchical topology for network-on-chip

As the number of modules in System-on-Chip (SoC) increases, the topology is more likely to suffer from excessive end-to-end hop-counts, causing an increase of power consumption and area overhead. Concerning this issue, a novel Mesh-based Hierarchical topology called CHMesh is proposed, which is divided into two levels. The bottom level is interconnected with Mesh and divided into several regions, so as to guarantee communications of adjacent nodes, and the upper level employs intermediate nodes to promote the interconnection among different bottom routing regions with CMesh, so as to decrease the network diameter. Correspondingly, this article elaborates on a shortest-path CHXY routing algorithm, which has a low complexity and can realize deadlock avoidance. Performance analysis and experimental results demonstrate that, compared with traditional Mesh and Ref-Mesh, the CHMesh can increase the average throughput by about 60% and 10% respectively under non-uniform traffic patterns, presenting more advantages on large-scale NoC.