A 14-bit 200-Ms/s SHA-Less Pipelined ADC with Aperture Error Reduction

被引：0
|
作者：
Yang, Peilin [1 ]
Wang, Xiao [1 ]
Wang, Chengwei [1 ]
Li, Fule [1 ]
Jiang, Hanjun [1 ]
Wang, Zhihua [1 ]
机构：
[1] Institute of Microelectronics, Tsinghua University, Beijing,100084, China
来源：
IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 2020年 / 28卷 / 09期
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页码：2004 / 2013
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