SafeTPU: A Verifiably Secure Hardware Accelerator for Deep Neural Networks

被引：0
|
作者：
Mera Collantes, Maria I. [1 ]
Ghodsi, Zahra [1 ]
Garg, Siddharth [1 ]
机构：
[1] New York University, Department of Electrical and Computer Engineering, United States
来源：
Proceedings of the IEEE VLSI Test Symposium | 2020年 / 2020-April卷
关键词：
Area overhead - Fault injection attacks - Hardware accelerators - High probability - Interactive proofs - Secure computation - Space and time - State of the art;
D O I：
9107564
中图分类号：
学科分类号：
摘要：
26
引用
收藏
相关论文
共 50 条
  • [1] SafeTPU: A Verifiably Secure Hardware Accelerator for Deep Neural Networks
    Collantes, Maria I. Mera
    Ghodsi, Zahra
    Garg, Siddharth
    2020 IEEE 38TH VLSI TEST SYMPOSIUM (VTS 2020), 2020,
  • [2] Hardware Accelerator for Adversarial Attacks on Deep Learning Neural Networks
    Guo, Haoqiang
    Peng, Lu
    Zhang, Jian
    Qi, Fang
    Duan, Lide
    2019 TENTH INTERNATIONAL GREEN AND SUSTAINABLE COMPUTING CONFERENCE (IGSC), 2019,
  • [3] A Hardware Accelerator Based on Quantized Weights for Deep Neural Networks
    Sreehari, R.
    Deepu, Vijayasenan
    Arulalan, M. R.
    EMERGING RESEARCH IN ELECTRONICS, COMPUTER SCIENCE AND TECHNOLOGY, ICERECT 2018, 2019, 545 : 1079 - 1091
  • [4] In-Memory Computing Based Hardware Accelerator Module for Deep Neural Networks
    Appukuttan, Allen
    Thomas, Emmanuel
    Nair, Harinandan R.
    Hemanth, S.
    Dhanaraj, K. J.
    Azeez, Maleeha Abdul
    2022 IEEE 19TH INDIA COUNCIL INTERNATIONAL CONFERENCE, INDICON, 2022,
  • [5] LACC: a hardware and software co-design accelerator for deep neural networks
    Yu Y.
    Zhi T.
    Zhou S.
    High Technology Letters, 2021, 27 (01) : 62 - 67
  • [6] LACC:a hardware and software co-design accelerator for deep neural networks
    于涌
    Zhi Tian
    Zhou Shengyuan
    HighTechnologyLetters, 2021, 27 (01) : 62 - 67
  • [7] LUPULUS: A FLEXIBLE HARDWARE ACCELERATOR FOR NEURAL NETWORKS
    Kristensen, Andreas Toftegaard
    Giterman, Robert
    Balatsoukas-Stimming, Alexios
    Burg, Andreas
    2020 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH, AND SIGNAL PROCESSING, 2020, : 1608 - 1612
  • [8] Implementation of artificial neural networks on a reconfigurable hardware accelerator
    Porrmann, M
    Witkowski, U
    Kalte, H
    Rückert, U
    10TH EUROMICRO WORKSHOP ON PARALLEL, DISTRIBUTED AND NETWORK-BASED PROCESSING, PROCEEDINGS, 2002, : 243 - 250
  • [9] TileNET: Hardware accelerator for ternary Convolutional Neural Networks
    Eetha, Sagar
    Sruthi, P. K.
    Pant, Vibha
    Vikram, Sai
    Mody, Mihir
    Purnaprajna, Madhura
    MICROPROCESSORS AND MICROSYSTEMS, 2021, 83
  • [10] An Efficient Hardware Accelerator for Sparse Transformer Neural Networks
    Fang, Chao
    Guo, Shouliang
    Wu, Wei
    Lin, Jun
    Wang, Zhongfeng
    Hsu, Ming Kai
    Liu, Lingzhi
    2022 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 22), 2022, : 2670 - 2674
12345