SafeTPU: A Verifiably Secure Hardware Accelerator for Deep Neural Networks

被引：0
|
作者：
Mera Collantes, Maria I. [1 ]
Ghodsi, Zahra [1 ]
Garg, Siddharth [1 ]
机构：
[1] New York University, Department of Electrical and Computer Engineering, United States
来源：
Proceedings of the IEEE VLSI Test Symposium | 2020年 / 2020-April卷
关键词：
Area overhead - Fault injection attacks - Hardware accelerators - High probability - Interactive proofs - Secure computation - Space and time - State of the art;
D O I：
9107564
中图分类号：
学科分类号：
摘要：
26
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