SafeTPU: A Verifiably Secure Hardware Accelerator for Deep Neural Networks

被引：0
|
作者：
Mera Collantes, Maria I. [1 ]
Ghodsi, Zahra [1 ]
Garg, Siddharth [1 ]
机构：
[1] New York University, Department of Electrical and Computer Engineering, United States
来源：
Proceedings of the IEEE VLSI Test Symposium | 2020年 / 2020-April卷
关键词：
Area overhead - Fault injection attacks - Hardware accelerators - High probability - Interactive proofs - Secure computation - Space and time - State of the art;
D O I：
9107564
中图分类号：
学科分类号：
摘要：
26
引用
收藏
相关论文
共 50 条
  • [21] Hardware Architecture Exploration for Deep Neural Networks
    Wenqi Zheng
    Yangyi Zhao
    Yunfan Chen
    Jinhong Park
    Hyunchul Shin
    Arabian Journal for Science and Engineering, 2021, 46 : 9703 - 9712
  • [22] Formal Verification of Deep Neural Networks in Hardware
    Saji, Sincy Ann
    Agrawal, Shreyansh
    Sood, Surinder
    2022 IEEE WOMEN IN TECHNOLOGY CONFERENCE (WINTECHCON): SMARTER TECHNOLOGIES FOR A SUSTAINABLE AND HYPER-CONNECTED WORLD, 2022,
  • [23] Secure and Verifiable Inference in Deep Neural Networks
    Xu, Guowen
    Li, Hongwei
    Ren, Hao
    Sun, Jianfei
    Xu, Shengmin
    Ning, Jianting
    Yang, Haomiao
    Yang, Kan
    Deng, Robert H.
    36TH ANNUAL COMPUTER SECURITY APPLICATIONS CONFERENCE (ACSAC 2020), 2020, : 784 - 797
  • [24] Data multiplexed and hardware reused architecture for deep neural network accelerator
    Raut, Gopal
    Biasizzo, Anton
    Dhakad, Narendra
    Gupta, Neha
    Papa, Gregor
    Vishvakarma, Santosh Kumar
    NEUROCOMPUTING, 2022, 486 : 147 - 159
  • [25] End-to-End Hardware Accelerator for Deep Convolutional Neural Network
    Chang, Tian-Sheuan
    2018 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), 2018,
  • [26] BSHIFT: A Low Cost Deep Neural Networks Accelerator
    Yu, Yong
    Zhi, Tian
    Zhou, Xuda
    Liu, Shaoli
    Chen, Yunji
    Cheng, Shuyao
    INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING, 2019, 47 (03) : 360 - 372
  • [27] An Efficient Hardware Accelerator for Block Sparse Convolutional Neural Networks on FPGA
    Yin, Xiaodi
    Wu, Zhipeng
    Li, Dejian
    Shen, Chongfei
    Liu, Yu
    IEEE EMBEDDED SYSTEMS LETTERS, 2024, 16 (02) : 158 - 161
  • [28] Learning accelerator of deep neural networks with logarithmic quantization
    Ueki, Takeo
    Iwai, Keisuke
    Matsubara, Takashi
    Kurokawa, Takakazu
    2018 7TH INTERNATIONAL CONGRESS ON ADVANCED APPLIED INFORMATICS (IIAI-AAI 2018), 2018, : 634 - 638
  • [29] Hardware Flexible Systolic Architecture for Convolution Accelerator in Convolutional Neural Networks
    Aguirre-Alvarez, Paulo Aaron
    Diaz-Carmona, Javier
    Arredondo-Velazquez, Moises
    2022 45TH INTERNATIONAL CONFERENCE ON TELECOMMUNICATIONS AND SIGNAL PROCESSING, TSP, 2022, : 305 - 309
  • [30] A FPGA-based Hardware Accelerator for Multiple Convolutional Neural Networks
    Yao, Yuchen
    Duan, Qinghua
    Zhang, Zhiqian
    Gao, Jiabao
    Wang, Jian
    Yang, Meng
    Tao, Xinxuan
    Lai, Jinmei
    2018 14TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT), 2018, : 1075 - 1077
12345