Fast-Locking Phase Locked Loop Dominated by SMC at VCO Voltage Tuning End

被引：0

作者：

Pu, Hongping ^{[1
,3
]}

Yang, Shiyong ^{[2
,3
]}

Xiong, Xingzhong ^{[2
,3
]}

Liu, Yongchun ^{[2
,3
]}

He, Jian ^{[3
,4
]}

Zheng, Xiaoxia ^{[3
,5
]}

机构：

[1] Chengdu Aeronaut Polytech, Sch Unmanned Aerial Vehicles Ind, Chengdu 610100, Sichuan, Peoples R China

[2] Sichuan Univ Sci & Engn, Sch Automat & Informat Engn, Yibin 644005, Sichuan, Peoples R China

[3] Sichuan Univ Sci & Engn, Artificial Intelligence Key Lab Sichuan Prov, Yibin 644005, Sichuan, Peoples R China

[4] Univ Elect Sci & Technol China UESTC, Yibin Inst, Yibin 644005, Sichuan, Peoples R China

[5] Chengdu Aeronaut Polytech, Sch Automot Engn, Chengdu 610100, Sichuan, Peoples R China

来源：

IEEE ACCESS | 2024年 / 12卷

关键词：

Voltage-controlled oscillators; Phase locked loops; Voltage control; Linear systems; Tuning; Switches; Charge pumps; Sliding mode control; Phase locked loop; sliding mode control; voltage control; PLL;

D O I：

10.1109/ACCESS.2024.3442291

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

The presented fast-locking phase-locked loop (PLL) approach, driven by sliding mode control (SMC), aims to maintain defined design parameters and system stability while achieving faster frequency switching. By adding the SMC output control voltage to the tuning terminal of the voltage controlled oscillator (VCO), the PLL system achieves a higher absolute rate of change of the VCO output frequency during frequency hopping. Simulation results in Simulink demonstrate a significant reduction in locking time, from 40 mu s in the conventional PLL to 5 mu s in the proposed PLL, under identical conditions of loop bandwidth and charge pump current.

引用

页码：112135 / 112143

页数：9

共 50 条

[41] A 200 MHz-to-1.4 GHz fast-locking pulse width control loop
Abrishamifar, Adib
Navidi, Mir Mohammad
Karimi, Yasha
INTERNATIONAL JOURNAL OF ELECTRONICS, 2014, 101 (03) : 341 - 353
[42] Integrated Phase Locked Loop and ILFD with VCO for Robotics Transmitter
Lai, Wen-Cheng
2018 IEEE INTERNATIONAL CONFERENCE ON CONSUMER ELECTRONICS-TAIWAN (ICCE-TW), 2018,
[43] A 0.95-TO-5.28 GHZ FAST LOCKING AND POWER EFFICIENT DIGITAL PHASE LOCKED LOOP
Mohammed, Reham I. A.
Abdelghany, Mahmoud A.
Khalaf, Ashraf A. M.
Hamed, Hesham F. A.
PROCEEDINGS OF 2022 39TH NATIONAL RADIO SCIENCE CONFERENCE (NRSC'2022), 2022, : 264 - 272
[44] A Broadband Phase-locked Ka-band Single-Tuning VCO with Reconfigurable Loop Filters
Kuo, Yue-Fang
Chiong, Chau-Ching
Hwang, Yuh-Jing
ASIA-PACIFIC MICROWAVE CONFERENCE 2011, 2011, : 773 - 776
[45] A Fast-Locking Wide-Range All-Digital Delay-Locked loop with a Starting SAR-Bit Prediction Mechanism
Yao, Chia-Yu
Ho, Yung-Hsiang
2013 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION, AND TEST (VLSI-DAT), 2013,
[46] Low Noise and Fast Locking Phase Locked Loop Using a Variable Delay Element in the Phase Frequency Detector
Nanda, Umakanta
Acharya, Debiprasad Priyabrata
Patra, Sarat Kumar
JOURNAL OF LOW POWER ELECTRONICS, 2014, 10 (01) : 53 - 57
[47] A Fast-Locking Wide-Range All-Digital Delay-Locked loop with a Starting SAR-Bit Prediction Mechanism
Yao, Chia-Yu
Ho, Yung-Hsiang
2013 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION, AND TEST (VLSI-DAT), 2013,
[48] Fast-locking PLL based on a novel PFD-CP structure and reconfigurable loop filter
Abolhasani, Alireza
Mousazadeh, Morteza
Khoei, Abdollah
IET CIRCUITS DEVICES & SYSTEMS, 2020, 14 (08) : 1235 - 1242
[49] A design of fast-locking without overshoot frequency-locked servo system, by fuzzy control technique
Chen, LR
Hsieh, GC
Lee, HM
JOURNAL OF THE CHINESE INSTITUTE OF ENGINEERS, 2004, 27 (01) : 147 - 151
[50] A wide frequency range delay line for fast-locking and low power delay-locked-loops
Estebsari, Motahhareh
Gholami, Mohammad
Ghahramanpour, Mohammad Javad
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2017, 90 (02) : 427 - 434

← 1 2 3 4 5 →