Fast-Locking Phase Locked Loop Dominated by SMC at VCO Voltage Tuning End

被引：0

作者：

Pu, Hongping ^{[1
,3
]}

Yang, Shiyong ^{[2
,3
]}

Xiong, Xingzhong ^{[2
,3
]}

Liu, Yongchun ^{[2
,3
]}

He, Jian ^{[3
,4
]}

Zheng, Xiaoxia ^{[3
,5
]}

机构：

[1] Chengdu Aeronaut Polytech, Sch Unmanned Aerial Vehicles Ind, Chengdu 610100, Sichuan, Peoples R China

[2] Sichuan Univ Sci & Engn, Sch Automat & Informat Engn, Yibin 644005, Sichuan, Peoples R China

[3] Sichuan Univ Sci & Engn, Artificial Intelligence Key Lab Sichuan Prov, Yibin 644005, Sichuan, Peoples R China

[4] Univ Elect Sci & Technol China UESTC, Yibin Inst, Yibin 644005, Sichuan, Peoples R China

[5] Chengdu Aeronaut Polytech, Sch Automot Engn, Chengdu 610100, Sichuan, Peoples R China

来源：

IEEE ACCESS | 2024年 / 12卷

关键词：

Voltage-controlled oscillators; Phase locked loops; Voltage control; Linear systems; Tuning; Switches; Charge pumps; Sliding mode control; Phase locked loop; sliding mode control; voltage control; PLL;

D O I：

10.1109/ACCESS.2024.3442291

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

The presented fast-locking phase-locked loop (PLL) approach, driven by sliding mode control (SMC), aims to maintain defined design parameters and system stability while achieving faster frequency switching. By adding the SMC output control voltage to the tuning terminal of the voltage controlled oscillator (VCO), the PLL system achieves a higher absolute rate of change of the VCO output frequency during frequency hopping. Simulation results in Simulink demonstrate a significant reduction in locking time, from 40 mu s in the conventional PLL to 5 mu s in the proposed PLL, under identical conditions of loop bandwidth and charge pump current.

引用

页码：112135 / 112143

页数：9

共 50 条

[1] A fast-locking digital phase-locked loop
Wagdy, Mahmoud Fawzy
Vaishnava, Srishti
THIRD INTERNATIONAL CONFERENCE ON INFORMATION TECHNOLOGY: NEW GENERATIONS, PROCEEDINGS, 2006, : 742 - +
[2] A low-noise and fast-locking phase-locked loop
Shahruz, SM
PROCEEDINGS OF THE 2003 AMERICAN CONTROL CONFERENCE, VOLS 1-6, 2003, : 2407 - 2412
[3] Low-noise and fast-locking phase-locked loop
Shahruz, SM
REVIEW OF SCIENTIFIC INSTRUMENTS, 2002, 73 (12): : 4347 - 4353
[4] A Novel Flash Fast-Locking Digital Phase-Locked Loop
Wagdy, Mahmoud Fawzy
Cabrales, Brandon Casey
PROCEEDINGS OF THE 2009 SIXTH INTERNATIONAL CONFERENCE ON INFORMATION TECHNOLOGY: NEW GENERATIONS, VOLS 1-3, 2009, : 47 - 52
[5] Frequency presetting and phase error detection technique for fast-locking phase-locked loop
Kao, Shao-Ku
MICROELECTRONICS JOURNAL, 2014, 45 (04) : 375 - 381
[6] A novel flash fast-locking digital phase-locked loop: design and simulations
Wagdy, M. F.
Cabrales, B. C.
IET CIRCUITS DEVICES & SYSTEMS, 2009, 3 (05) : 280 - 290
[7] A fast-locking bang-bang phase-locked loop with adaptive loop gain controller
Jincheng Yang
Zhao Zhang
Nan Qi
Liyuan Liu
Jian Liu
Nanjian Wu
Journal of Semiconductors, 2018, (12) : 172 - 178
[8] A Fast-Locking All-Digital Phase-Locked Loop With Dynamic Loop Bandwidth Adjustment
Lin, Jung-Mao
Yang, Ching-Yuan
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2015, 62 (10) : 2411 - 2422
[9] A fast-locking bang-bang phase-locked loop with adaptive loop gain controller
Yang, Jincheng
Zhang, Zhao
Qi, Nan
Liu, Liyuan
Liu, Jian
Wu, Nanjian
JOURNAL OF SEMICONDUCTORS, 2018, 39 (12)
[10] A fast-locking bang-bang phase-locked loop with adaptive loop gain controller
Jincheng Yang
Zhao Zhang
Nan Qi
Liyuan Liu
Jian Liu
Nanjian Wu
Journal of Semiconductors, 2018, 39 (12) : 172 - 178

← 1 2 3 4 5 →