A 5.80 ns, 22.77 fJ, Energy Efficient Level Shifter Using Auto Switch Logic

Level shifters are essential in ultra-low-power analog mixed-signal systems. This brief introduces a level shifter with auto-switch logic. The auto switch logic can automatically alter the connection mode of the pull-up network during transition phases. This approach allows the level shifter, when employing the current limiter, to preserve its strong pull-down capabilities while selecting the optimal path for cutting off the pull-up transistor. Additionally, other optimization strategies, such as pass transistors and a split inverter, are employed in this paper. The proposed level shifter is designed and simulated using a 65 nm multi-threshold CMOS process. In the 0.3 V to 1.2 V level conversion with a 1 MHz input frequency, the delay of the proposed level shifter is 5.80 ns, the energy per transition is 22.77 fJ, and the leakage power is 1.02 nW. When the input signal is relaxed to 1 KHz, the proposed level shifter achieves a minimum voltage of 140 mV.