A New Semi-Analytical Model for Erase Transients of 3-D Gate-All-Around (GAA) NAND Flash Memories

被引：0
|
作者：
Yoo, Jinil [1 ]
Choi, Haechan [1 ]
Shin, Hyungcheol [1 ]
机构：
[1] Seoul Natl Univ, Interuniv Semicond Res Ctr, Dept Elect & Comp Engn, Seoul 08826, South Korea
来源：
IEEE TRANSACTIONS ON ELECTRON DEVICES | 2024年 / 71卷 / 11期
关键词：
Mathematical models; Logic gates; Numerical models; Electron traps; Tunneling; Transient analysis; Electrons; 3-D nand flash memory; amphoteric trap model (ATM); back tunneling; continuity equation; threshold voltage; RETENTION; OPERATION; DYNAMICS; OXIDE;
D O I：
10.1109/TED.2024.3454284
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this article, we introduce a new semi-analytical model to calculate the erase (ERS) transients of 3-D gate-all-around (GAA) nand flash memories. A previously proposed program (PGM) model is revised by adopting the amphoteric trap model (ATM). Injection/escape/back tunneling components are added and the influences of each are investigated. The proposed model makes a better fit with experimental data than the previous model and also successfully implements the back tunneling component.
引用
收藏
页码：6665 / 6671
页数：7
相关论文
共 48 条
  • [31] Compact Modeling of Cross-Sectional Scaling in Gate-All-Around FETs: 3-D to 1-D Transition
    Dasgupta, Avirup
    Rastogi, Priyank
    Agarwal, Amit
    Hu, Chenming
    Chauhan, Yogesh Singh
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2018, 65 (03) : 1094 - 1100
  • [32] A Process-Aware Compact Model for GIDL-Assisted Erase Optimization of 3-D V-NAND Flash Memory
    Kim, Yohan
    Kim, SoYoung
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2023, 70 (04) : 1664 - 1670
  • [33] Semi-Analytical 3-D Magnetic Charge Model for Force Calculation of a Transverse Flux Machine
    Kremers, M. F. J.
    Casteren, D. T. E. H. v.
    Paulides, J. J. H.
    Lomonova, E. A.
    2015 TENTH INTERNATIONAL CONFERENCE ON ECOLOGICAL VEHICLES AND RENEWABLE ENERGIES (EVER), 2015,
  • [34] Predictive 3-D Modeling of Parasitic Gate Capacitance in Gate-all-Around Cylindrical Silicon Nanowire MOSFETs (vol 59, pg 3, 2012)
    Zou, Jibin
    Xu, Qiumin
    Luo, Jieying
    Wang, Runsheng
    Huang, Ru
    Wang, Yangyuan
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2012, 59 (03) : 867 - 867
  • [35] Scatterometry-Based Calibration of a 3D Virtual Fabrication Model for Gate-All-Around Devices
    Feng, Ye
    Ervin, Joseph
    Lu, Yang
    Woo, Anthony
    Coogans, Martyn
    Chakarov, Ivan
    Fried, David
    DESIGN-PROCESS-TECHNOLOGY CO-OPTIMIZATION XV, 2021, 11614
  • [36] Optimizing read disturb phenomenon with new read scheme by partial-boosting channel in 3-D NAND Flash memories
    Ahn, Sangmin
    Shin, Hyungcheol
    IEICE ELECTRONICS EXPRESS, 2021, 18 (19):
  • [37] New Read Schemes to Reduce Read Disturbance Due to HCI in Full Boosting Channel 3-D NAND Flash Memories
    Jo, Hyungjun
    Shin, Hyungcheol
    2021 SILICON NANOELECTRONICS WORKSHOP (SNW), 2021, : 39 - 40
  • [38] Non-Linear 3-D Semi-Analytical Model for an Axial-Flux Reluctance Magnetic Coupling
    Dorget, Remi
    Lubin, Thierry
    IEEE TRANSACTIONS ON ENERGY CONVERSION, 2022, 37 (03) : 2037 - 2047
  • [39] Two-dimensional (2D) analytical investigation of an n-type junctionless gate-all-around tunnel field-effect transistor (JL GAA TFET)
    Ajay
    Narang, Rakhi
    Saxena, Manoj
    Gupta, Mridula
    JOURNAL OF COMPUTATIONAL ELECTRONICS, 2018, 17 (02) : 713 - 723
  • [40] Two-dimensional (2D) analytical investigation of an n-type junctionless gate-all-around tunnel field-effect transistor (JL GAA TFET)
    Rakhi Ajay
    Manoj Narang
    Mridula Saxena
    Journal of Computational Electronics, 2018, 17 : 713 - 723
12345