Network Adapter for Secure Networks-on-Chip

被引：0

作者：

Haase, Julian ^{[1
]}

Volkens, Nico ^{[1
]}

Goehringer, Diana ^{[1
,2
]}

机构：

[1] Tech Univ Dresden, Chair Adapt Dynam Syst, Dresden, Germany

[2] Tech Univ Dresden, Ctr Tactile Internet Human Loop CeTI, Dresden, Germany

来源：

2024 IEEE INTERNATIONAL PARALLEL AND DISTRIBUTED PROCESSING SYMPOSIUM WORKSHOPS, IPDPSW 2024 | 2024年

关键词：

Network-on-Chip; Network Adapter; Security; Lightweight Encryption; MPSoC;

D O I：

10.1109/IPDPSW63119.2024.00052

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This work explores the security challenges presented by Hardware Trojans (HTs) in Network-on-Chip (NoC) and Multiprocessor System-on-Chip (MPSoC) architectures. It proposes a Network Adapter (NA) approach to mitigate these risks, thereby enhancing the security and reliability of the overall system. The NA uses Authenticated Encryption to maintain confidentiality and ensure packet integrity. In addition, retransmissions recover corrupted or deleted packets, allowing a compromised system with an HT to remain operational. The goal of this paper is to provide insights into the potential benefits and challenges of adding such NA and thus contribute to the development of secure NoC and MPSoCs for future embedded systems.

引用

页码：192 / 192

页数：1

共 50 条

[41] Nanophotonic Devices for Optical Networks-On-Chip
Van Thourhout, D.
O'Connor, I.
Scandurra, A.
Liu, L.
Bogaerts, W.
Selvaraja, S.
Roelkens, G.
2009 CONFERENCE ON LASERS AND ELECTRO-OPTICS AND QUANTUM ELECTRONICS AND LASER SCIENCE CONFERENCE (CLEO/QELS 2009), VOLS 1-5, 2009, : 295 - +
[42] A Hybrid Optoelectronic Networks-on-Chip Architecture
Tan, Xianfang
Yang, Mei
Zhang, Lei
Wang, Xiaohang
Jiang, Yingtao
JOURNAL OF LIGHTWAVE TECHNOLOGY, 2014, 32 (05) : 991 - 998
[43] Automatic ILP-based Firewall Insertion for Secure Application-specific Networks-on-Chip
Hu, Yong
Mueller-Gritschneder, Daniel
Sepulveda, Martha Johanna
Gogniat, Guy
Schlichtmann, Ulf
2015 NINTH INTERNATIONAL WORKSHOP ON INTERCONNECTION NETWORK ARCHITECTURES: ON-CHIP, MULTI-CHIP (INA-OCMC), 2015, : 9 - 12
[44] An Analytical Latency Model for Networks-on-Chip
Kiasari, Abbas Eslami
Lu, Zhonghai
Jantsch, Axel
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2013, 21 (01) : 113 - 123
[45] The Need for Reconfigurable Routers in Networks-on-Chip
Matos, Debora
Concatto, Caroline
Carro, Luigi
Kastensmidt, Fernanda
Susin, Altamiro
RECONFIGURABLE COMPUTING: ARCHITECTURES, TOOLS AND APPLICATIONS, 2009, 5453 : 275 - 280
[46] Power Characteristics of Asynchronous Networks-on-Chip
Rashed, Maher
Abd El Ghany, Mohamed A.
Ismail, Mohammed
2011 IEEE INTERNATIONAL SOC CONFERENCE (SOCC), 2011, : 160 - 165
[47] An Approach for Multicast Routing in Networks-on-Chip
Prasad, M. Lakshmi
Das, Shirshendu
Kapoor, Hemangee K.
2014 INTERNATIONAL CONFERENCE ON INFORMATION TECHNOLOGY (ICIT), 2014, : 299 - 304
[48] ICARO: Congestion Isolation in Networks-On-Chip
Escamilla, Jose V.
Flich, Jose
Javier Garcia, Pedro
2014 EIGHTH IEEE/ACM INTERNATIONAL SYMPOSIUM ON NETWORKS-ON-CHIP (NOCS), 2014, : 159 - 166
[49] Buffer implementation for proteo networks-on-chip
Saastamoinen, I
Alho, M
Nurmi, J
PROCEEDINGS OF THE 2003 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II: COMMUNICATIONS-MULTIMEDIA SYSTEMS & APPLICATIONS, 2003, : 113 - 116
[50] Introduction to the special section on networks-on-chip
Marculescu, Radu
IEEE TRANSACTIONS ON COMPUTERS, 2008, 57 (09) : 1153 - 1155

← 1 2 3 4 5 →