A Novel Double-Sided Etching and Electroplating Fabrication Scheme for Coaxial Through-Silicon-Vias in 3-D Integration

被引:0
|
作者
Chen, Zhiming [1 ]
Chen, Xuyan [1 ]
Wang, Han [1 ]
Cai, Ziru [1 ]
Xiong, Miao [1 ]
Hao, Yigang [1 ]
Ding, Yingtao [1 ]
Zhang, Ziyue [1 ,2 ]
机构
[1] Beijing Inst Technol, Sch Integrated Circuits & Elect, Beijing 100081, Peoples R China
[2] Beijing Inst Technol, Chongqing Inst Microelect & Microsyst, Chongqing 400030, Peoples R China
基金
中国国家自然科学基金; 中国博士后科学基金;
关键词
Through-silicon vias; Conductors; Insulators; Fabrication; Silicon; Electrochemical deposition; Radio frequency; 2.5-D/3-D heterogeneous integration; benzocyclobutene (BCB) insulator; coaxial through-silicon-via (TSV); double-sided microfabrication; ultrawideband; MICROSYSTEMS;
D O I
10.1109/TED.2024.3438677
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Compared to conventional through-silicon-via (TSV) technology, coaxial TSVs can provide better radio frequency (RF) transmission performance in terms of reduced transmission loss and enhanced impedance matching in 2.5-D/3-D heterogeneous integration of RF microsystems. This article presents a novel fabrication scheme for coaxial TSVs comprised of Cu-pillar inner conductors, annular benzocyclobutene (BCB) insulators, and annular Cu outer conductors. Complete Cu conductors are achieved by the proposed double-sided etching and electroplating method, in which the outer and inner conductors are fabricated from the front and back sides of the wafer, respectively. Besides, a thick BCB insulator without voids is realized based on the vacuum-assisted spin-filling technique. Due to the good feasibility of the fabrication processes, the dimensions of the coaxial TSV can be flexibly designed to meet the requirements for impedance matching. Coaxial TSVs with a height of 85 mu m, an inner conductor diameter of 45 mu m, and an insulator thickness of 53 mu m are successfully fabricated. Measurement results show that the TSVs exhibit a low leakage current between the inner and outer conductors of 1.28 pA at 20 V, and the return loss and insertion loss are better than - 16 and - 0.35 dB up to 40 GHz, respectively. Such compact and low-loss coaxial TSV structure together with its fabrication scheme facilitates the miniaturized, high-density, and high-performance 2.5-D/3-D heterogeneous integration of microsystems at RF and millimeter-wave (MMW) frequencies.
引用
收藏
页码:6249 / 6253
页数:5
相关论文
共 50 条
  • [21] Thermal reliability analysis and optimization of polymer insulating through-silicon-vias (TSVs) for 3D integration
    Zhong ShunAn
    Wang ShiWei
    Chen QianWen
    Ding YingTao
    SCIENCE CHINA-TECHNOLOGICAL SCIENCES, 2014, 57 (01) : 128 - 135
  • [22] Thermal reliability analysis and optimization of polymer insulating through-silicon-vias (TSVs) for 3D integration
    ShunAn Zhong
    ShiWei Wang
    QianWen Chen
    YingTao Ding
    Science China Technological Sciences, 2014, 57 : 128 - 135
  • [23] Thermal reliability analysis and optimization of polymer insulating through-silicon-vias(TSVs) for 3D integration
    ZHONG ShunAn
    WANG ShiWei
    CHEN QianWen
    DING YingTao
    Science China(Technological Sciences), 2014, (01) : 128 - 135
  • [24] Magnetically-enhanced capacitively-coupled plasma etching for 300 mm wafer-scale fabrication of Cu through-silicon-vias for 3D logic integration
    Teh, W. H.
    Caramto, R.
    Arkalgud, S.
    Saito, T.
    Maruyama, K.
    Maekawa, K.
    PROCEEDINGS OF THE 2009 IEEE INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE, 2009, : 53 - +
  • [25] Double-Sided, Double-Type-Column 3-D Detectors: Design, Fabrication, and Technology Evaluation
    Zoboli, Andrea
    Boscardin, Maurizio
    Bosisio, Luciano
    Dalla Betta, Gian-Franco
    Piemonte, Claudio
    Ronchin, Sabina
    Zorzi, Nicola
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2008, 55 (05) : 2775 - 2784
  • [26] Thermal reliability analysis and optimization of polymer insulating through-silicon-vias(TSVs) for 3D integration
    ZHONG ShunAn
    WANG ShiWei
    CHEN QianWen
    DING YingTao
    Science China(Technological Sciences), 2014, 57 (01) : 128 - 135
  • [27] Energy Release Rate Estimation for Through Silicon Vias in 3-D IC Integration
    Hsieh, Ming-Che
    Wu, Sheng-Tsai
    Wu, Chung-Jung
    Lau, John H.
    IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2014, 4 (01): : 57 - 65
  • [28] Simulation results from double-sided 3-D detectors
    Pennicard, D.
    Pellegrini, G.
    Lozano, M.
    Bates, R.
    Parkes, C.
    O'Shea, V.
    Wright, V.
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2007, 54 (04) : 1435 - 1443
  • [29] Optimized lithography process for through-silicon vias-fabrication using a double-sided (structured) photomask for mask aligner lithography
    Weichelt, Tina
    Stuerzebecher, Lorenz
    Zeitner, Uwe D.
    JOURNAL OF MICRO-NANOLITHOGRAPHY MEMS AND MOEMS, 2015, 14 (03):
  • [30] Thermal-Aware Modeling and Analysis for a Power Distribution Network Including Through-Silicon-Vias in 3-D ICs
    Zhu, Weijun
    Dong, Gang
    Yang, Yintang
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2019, 38 (07) : 1278 - 1290