Novel Multi-Level Coding and Architecture Enabling Fast Random Access for Flash Memory

被引：0

作者：

Shibata, Noboru ^{[1
]}

Uchikawa, Hironori ^{[1
]}

Shibuya, Taira ^{[2
]}

Inoue, Hirofumi ^{[3
]}

机构：

[1] Kioxia Corp, Inst Memory Technol Res & Dev, Tokyo, Japan

[2] Kioxia Corp, Memory Div, Tokyo, Japan

[3] Kioxia Corp, Memory Dev Strategy Div, Tokyo, Japan

来源：

2024 IEEE INTERNATIONAL MEMORY WORKSHOP, IMW | 2024年

关键词：

flash memory; storage class memory (SCM); random read latency; SLC (1bit/cell); X1.5 (3bit/2cell); MLC (2bit/cell); TLC (3bit/cell); QLC (4bit/cell); PLC (5bit/cell); HLC (6bit/cell);

D O I：

10.1109/IMW59701.2024.10536951

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This study introduces a novel multi-level coding and architecture designed to enhance random access time in multi-level flash memory. By employing a strategy of sharing and storing multi-level data across multiple memory cells, we address the challenge of increased read cycles typically associated with multi-level data. This architecture, which does not require new processes or materials, achieves one-cycle reading in MLC, equating its random access time with that of SLC, and ensures rapid random access in TLC.

引用

下载

页数：4

共 50 条

[41] Implementation of Data Search in Multi-Level NAND Flash Memory by Complementary Storage Scheme
Wang, Fei
Feng, Yang
Zhan, Xuepeng
Chen, Bing
Chen, Jiezhi
IEEE ELECTRON DEVICE LETTERS, 2020, 41 (08) : 1189 - 1192
[42] Improvement of the multi-level cell performance by a soft program method in flash memory devices
Park, Jong Kyung
Lee, Ki-Hong
Pyi, Seung Ho
Lee, Seok-Hee
Cho, Byung Jin
SOLID-STATE ELECTRONICS, 2014, 94 : 86 - 90
[43] Reliability Enhancement for Multi-level Cell NAND Flash Memory Using Error Asymmetry
Duc-Phuc Nguyen
Khoa Le Trung
Ghaffari, Fakhreddine
Declercq, David
PROCEEDINGS OF 2019 25TH ASIA-PACIFIC CONFERENCE ON COMMUNICATIONS (APCC), 2019, : 502 - 506
[44] Energy-aware data compression for multi-level cell (MLC) flash memory
Joo, Yongsoo
Cho, Youngjin
Shin, Donghwa
Chang, Naehyuck
2007 44TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2, 2007, : 716 - +
[45] Hitachi's multi-level 0.13-μm AG-AND flash memory
Anon
Hitachi Review, 2002, (SPEC):
[46] Memory Copies in Multi-Level Memory Systems
de Langen, Pepijn
Juurlink, Ben
2008 INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES AND PROCESSORS, 2008, : 281 - 286
[47] Parallel Random Access Memory in a Shared Memory Architecture
Tran Due Linh
de Souza-Daw, Tony
Thang Manh Hoang
Nguyen Tien Dzung
2014 IEEE FIFTH INTERNATIONAL CONFERENCE ON COMMUNICATIONS AND ELECTRONICS (ICCE), 2014, : 364 - 369
[48] Co-Optimization of Memory Access and Task Scheduling on MPSoC Architectures with Multi-Level Memory
He, Yi
Xue, Chun Jason
Xu, Cathy Qun
Sha, Edwin H. -M.
2010 15TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC 2010), 2010, : 93 - +
[49] A Novel Security Architecture Based on Multi-level Rule Expression Language
Souissi, Samih
Sliman, Layth
Charroux, Benoit
HYBRID INTELLIGENT SYSTEMS, HIS 2015, 2016, 420 : 259 - 269
[50] Multi-Level Secure JTAG Architecture
Pierce, Luke
Tragoudas, Spyros
2011 IEEE 17TH INTERNATIONAL ON-LINE TESTING SYMPOSIUM (IOLTS), 2011,

← 1 2 3 4 5 →