Novel Multi-Level Coding and Architecture Enabling Fast Random Access for Flash Memory

被引：0

作者：

Shibata, Noboru ^{[1
]}

Uchikawa, Hironori ^{[1
]}

Shibuya, Taira ^{[2
]}

Inoue, Hirofumi ^{[3
]}

机构：

[1] Kioxia Corp, Inst Memory Technol Res & Dev, Tokyo, Japan

[2] Kioxia Corp, Memory Div, Tokyo, Japan

[3] Kioxia Corp, Memory Dev Strategy Div, Tokyo, Japan

来源：

2024 IEEE INTERNATIONAL MEMORY WORKSHOP, IMW | 2024年

关键词：

flash memory; storage class memory (SCM); random read latency; SLC (1bit/cell); X1.5 (3bit/2cell); MLC (2bit/cell); TLC (3bit/cell); QLC (4bit/cell); PLC (5bit/cell); HLC (6bit/cell);

D O I：

10.1109/IMW59701.2024.10536951

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This study introduces a novel multi-level coding and architecture designed to enhance random access time in multi-level flash memory. By employing a strategy of sharing and storing multi-level data across multiple memory cells, we address the challenge of increased read cycles typically associated with multi-level data. This architecture, which does not require new processes or materials, achieves one-cycle reading in MLC, equating its random access time with that of SLC, and ensures rapid random access in TLC.

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页数：4

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