MIRRORING ATPG TECHNOLOGY FOR MULTI-CORE CHIPS

被引：0
|
作者：
Ouyang, Keqing [1 ,2 ]
Peng, Minqiang [1 ,2 ]
Zhou, Jitong [1 ,2 ]
Zhou, Guohua [1 ,2 ]
Wu, Youfa [1 ,2 ]
机构：
[1] State Key Lab Mobile Network & Mobile Multimedia, Shenzhen 518000, Peoples R China
[2] Sanechips Technol Co Ltd, Shenzhen 518000, Peoples R China
来源：
CONFERENCE OF SCIENCE & TECHNOLOGY FOR INTEGRATED CIRCUITS, 2024 CSTIC | 2024年
关键词：
DESIGNS; CAPTURE;
D O I：
10.1109/CSTIC61820.2024.10532089
中图分类号：
TP39 [计算机的应用];
学科分类号：
081203 ; 0835 ;
摘要：
Multi-core multiplexing scenarios are common in today's ultra-large-scale network system chips and large computing power chips such as CPUs and GPUs. To screen out chips with manufacturing defects and to improve product quality, the traditional automatic test pattern generation(ATPG) method requires large numbers of input and output(I/O) pins. In this paper, a novel idea called Mirroring ATPG is proposed to reduce the I/O resources and improve the efficiency of ATPG test.
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