Redundancy in multi-core memory-rich application-specific PIM chips

A trend of growing significance in the arena of advanced microprocessor chip design is the inclusion of multiple processor cores onto the same die with significant parts of the memory hierarchy. This is done to reduce both non-recurring design costs and power dissipation, and to get more computational capability and utilization out of the silicon. A side-effect, however is the opportunity to leverage the redundancy offered by these multiple cores to improve both die yield (and thus reduce chip costs) and the longevity of systems employing such chips. This paper discusses the key variables that go into the configuration of such multicore chips where the goal is complete integration with the memory hierarchy in a single part type. The emphasis of the study is on understanding how many cores, and of what complexity, are most appropriate.