Content-addressable memory using selective-charging and adaptive-discharging scheme for low-power hardware search engine

Single clock cycle access feature of content -addressable memory (CAM) suits well for high-speed parallel content search operation in data -intensive hardware search engines. The diverse applications span from accelerating databases and routing networks to processing images, implementing machine learning, processing biomedical data, and compressing data. Nevertheless, the CAM macro consumes significant energy due to the high switching of most match -lines (MLs), which comprise CAM words, during parallel access. Segmented ML schemes reduced power yet the cell and ML delay, and the extra sequential cycles affect search -speed. A novel selective -charging and adaptive -discharging (SCAD) scheme in the form of dynamic ML architecture is proposed to reduce CAM power consumption at no extra cycle cost. Additionally, a full -swing CAM cell forms the basis of storage and comparison -evaluation to lessen ML delay. Based on 45-nm technology under 1-V supply, the proposed 64 x 32 -bit and 256 x 144 -bit SCAD-CAM arrays dissipate only 0.45-0.46 fJ/bit/search energy and achieve high-speed. Compared to CAMs based on low -power ML schemes, viz., low -swing precharge, division and control, and master-slave, and the conventional CAM as baseline design, the SCAD-CAM reduces 13.49%- 89.35% energy -delay. The average -power reduction of 1.8 x -2.4 x establishes the SCAD-CAM as a promising memory architecture for emerging search -intensive applications involving large-scale data workloads.