A LOW NOISE FULL DIGITAL PHASE-LOCKED LOOP WITH FEEDTHROUGH SUPPRESSION TECHNOLOGY FOR RESONANT ACCELEROMETER

被引：1
|
作者：
Zhu, Bingchen [1 ,2 ,3 ]
Ma, Liangbo [1 ,3 ]
Xiong, Xingyin [1 ]
Zou, Xudong [1 ,2 ,3 ]
机构：
[1] Chinese Acad Sci, Aerosp Informat Res Inst, State Key Lab Transducer Technol, Beijing 100190, Peoples R China
[2] QiLu Aerosp Informat Res Inst, Jinan 250101, Peoples R China
[3] Univ Chinese Acad Sci, Sch Elect Elect & Commun Engn, Beijing 100049, Peoples R China
来源：
2024 IEEE INTERNATIONAL SYMPOSIUM ON INERTIAL SENSORS AND SYSTEMS, INERTIAL | 2024年
关键词：
digital; accelerometer; feedthrough;
D O I：
10.1109/INERTIAL60399.2024.10502048
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This study presents an integrated digital measurement and control system (DMCS) for the accelerometer, which combines resonator feedthrough prediction and elimination techniques. The bias instability in frequency measurement reaches 170ppt. This system makes the phase change of the accelerometer monotonous, enhancing the stability of the accelerometer.
引用
收藏
页数：4
相关论文
共 50 条
  • [21] JITTER REDUCTION OF A DIGITAL PHASE-LOCKED LOOP
    YAMASHITA, M
    TSUJI, T
    NISHIMURA, T
    MURATA, M
    NAMEKAWA, T
    PROCEEDINGS OF THE IEEE, 1976, 64 (11) : 1640 - 1641
  • [22] A digital phase-locked loop for frequency detection
    Werter, JM
    38TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, PROCEEDINGS, VOLS 1 AND 2, 1996, : 1252 - 1255
  • [23] A design method for digital phase-locked loop
    Ru Jiyuan
    Liu Yujia
    Xue Wei
    PROCEEDINGS OF THE 2015 4TH NATIONAL CONFERENCE ON ELECTRICAL, ELECTRONICS AND COMPUTER ENGINEERING ( NCEECE 2015), 2016, 47 : 1471 - 1475
  • [24] DIGITAL PHASE-LOCKED LOOP WITH JITTER BOUNDED
    WALTERS, SM
    TROUDET, T
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, 1989, 36 (07): : 980 - 987
  • [25] Markov model for digital phase-locked loop
    Samokhvalov, A.A.
    Kondrat'ev, A.V.
    Timofeev, A.A.
    Elektromagnitnye Volny i Elektronnye Systemy, 2005, 10 (06): : 47 - 55
  • [26] GRAPHICAL ANALYSIS OF A DIGITAL PHASE-LOCKED LOOP
    RUSSO, F
    IEEE TRANSACTIONS ON AEROSPACE AND ELECTRONIC SYSTEMS, 1979, 15 (01) : 88 - 94
  • [27] RESPONSE OF AN ALL DIGITAL PHASE-LOCKED LOOP
    GARODNICK, J
    GRECO, J
    SCHILLING, DL
    IEEE TRANSACTIONS ON COMMUNICATIONS, 1974, CO22 (06) : 751 - 764
  • [28] Digital Phase-Locked Loop and its Realization
    Kao, Tsai-Sheng
    Chen, Sheng-Chih
    Chang, Yuan-Chang
    Hou, Sheng-Yun
    Juan, Chang-Jung
    AIC '09: PROCEEDINGS OF THE 9TH WSEAS INTERNATIONAL CONFERENCE ON APPLIED INFORMATICS AND COMMUNICATIONS: RECENT ADVANCES IN APPLIED INFORMAT AND COMMUNICATIONS, 2009, : 415 - +
  • [29] PHASE NOISE AND TRANSIENT TIMES FOR A BINARY QUANTIZED DIGITAL PHASE-LOCKED LOOP IN WHITE GAUSSIAN NOISE
    CESSNA, JR
    LEVY, DM
    IEEE TRANSACTIONS ON COMMUNICATIONS, 1972, CO20 (02) : 94 - &
  • [30] A C-band low-noise frequency synthesizer based on digital phase-locked loop
    Yuan Xue-Lin
    Zhu Chang
    Yuan Nai-Chang
    2007 5TH INTERNATIONAL CONFERENCE ON MICROWAVE AND MILLIMETER WAVE TECHNOLOGY PROCEEDINGS, 2007, : 742 - +
12345