Massive MIMO Signal Detection using SRAM-based In-Memory Computing

This paper explores the use of static random access memory (SRAM)-based in-memory computing (IMC) architectures as signal detectors in massive multi-input multi-output (MIMO) wireless receivers. SRAM-based IMCs have demonstrated significant benefits in terms of energy efficiency and compute density over digital accelerators for deep learning workloads. However, their limited compute accuracy has hindered their application in other domains. Employing system-level models of the wireless channel and behavioral models of an SRAM -based IMC in 28nm CMOS process, we show that a symbol error rate (SER) < 10(-4) can be achieved for SNR > 19 dB when implementing zero forcing (ZF) or linear minimum mean square error (LMMSE) detectors on a SRAM-based IMC for a 128 x 16 MIMO uplink.