XNOR-SRAM: In-Memory Computing SRAM Macro for Binary/Ternary Deep Neural Networks

被引：0

作者：

Jiang, Zhewei ^{[1
]}

Yin, Shihui ^{[2
]}

Seok, Mingoo ^{[1
]}

Seo, Jae-sun ^{[2
]}

机构：

[1] Columbia Univ, New York, NY 10027 USA

[2] Arizona State Univ, Tempe, AZ 85287 USA

来源：

2018 IEEE SYMPOSIUM ON VLSI TECHNOLOGY | 2018年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We present an in-memory computing SRAM macro that computes XNOR-and-accumulate in binary/ternary deep neural networks on the bitline without row-by-row data access. It achieves 33X better energy and 300X better energy-delay product than digital ASIC, and also achieves significantly higher accuracy than prior in-SRAM computing macro (e.g., 98.3% vs. 90% for MNIST) by being able to support the mainstream DNN/CNN algorithms.

引用

页码：173 / 174

页数：2

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